Semiconductor device and manufacturing method of the same

ABSTRACT

A minute transistor is provided that includes a first insulator, a second insulator, a first, conductor, a second conductor, and third conductor, in which an angle is formed between a side surface of the first insulator and a top surface of the first conductor, and a length between the first conductor and a surface of the second conductor closest to the first conductor is at least greater than a length between the first conductor and the third conductor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.16/905,120, filed Jun. 18, 2020, now allowed, which is a continuation ofU.S. application Ser. No. 15/091,009, filed Apr. 5, 2016, now U.S. Pat.No. 10,693,013, which claims the benefit of foreign priorityapplications filed in Japan as Serial No. 2015-081993 on Apr. 13, 2015,and Serial No. 2015-082008 on Apr. 13, 2015, all of which areincorporated by reference.

TECHNICAL FIELD

The present invention relates to a transistor and a semiconductordevice, and a manufacturing method thereof, for example. The presentinvention relates to a display device, a light-emitting device, alighting device, a power storage device, a memory device, an imagingdevice, a processor, or an electronic device, for example. The presentinvention relates to a method for manufacturing a display device, aliquid crystal display device, a light-emitting device, a memory device,an imaging device, or an electronic device. The present inventionrelates to a driving method of a semiconductor device, a display device,a liquid crystal display device, a light-emitting device, a memorydevice, or an electronic device.

Note that one embodiment of the present invention is not limited to theabove technical field. The technical field of one embodiment of theinvention disclosed in this specification and the like relates to anobject, a method, or a manufacturing method. In addition, one embodimentof the present invention relates to a process, a machine, manufacture,or a composition of matter.

In this specification and the like, a semiconductor device generallymeans a device that can function by utilizing semiconductorcharacteristics. A display device, a light-emitting device, a lightingdevice, an electro-optical device, a semiconductor circuit, and anelectronic device include a semiconductor device in some cases.

BACKGROUND ART

In recent years, a transistor including an oxide semiconductor hasattracted attention. It is known that a transistor including an oxidesemiconductor has an extremely low leakage current in an off state. Forexample, a low-power CPU and the like utilizing the characteristics thata leakage current of the transistor including an oxide semiconductor islow is disclosed (see Patent Document 1).

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.    2012-257187

DISCLOSURE OF INVENTION

An object is to provide a minute transistor. Another object is toprovide a transistor with low parasitic capacitance. Another object isto provide a transistor with high frequency characteristics. Anotherobject is to provide a transistor with favorable electricalcharacteristics. Another object is to provide a transistor with stableelectrical characteristics. Another object is to provide a transistorwith low off-state current. Another object is to provide a noveltransistor. Another object is to provide a semiconductor deviceincluding the transistor. Another object is to provide a semiconductordevice which can operate at high speed. Another object is to provide anovel semiconductor device. Another object is to provide a moduleincluding the semiconductor device. Another object is to provide anelectronic device including the semiconductor device or the module.

Note that the descriptions of these objects do not disturb the existenceof other objects. In one embodiment of the present invention, there isno need to achieve all the objects. Other objects will be apparent fromand can be derived from the description of the specification, thedrawings, the claims, and the like.

One embodiment of the present invention is a semiconductor deviceincluding a semiconductor over a substrate, a first conductor and asecond conductor over the semiconductor, a first insulator over thefirst conductor and the second conductor, a second insulator over thesemiconductor, a third insulator over the second insulator, and a thirdconductor over the third insulator. The third insulator is in contactwith a side surface of the first insulator. The semiconductor includes afirst region where the semiconductor overlaps with a bottom surface ofthe first conductor, a second region where the semiconductor overlapswith a bottom surface of the second conductor, and a third region wherethe semiconductor overlaps with a bottom surface of the third conductor.The length between a top surface of the semiconductor and the bottomsurface of the third conductor is longer than the length between thefirst region and the third region.

One embodiment of the present invention is a semiconductor deviceincluding a semiconductor over a substrate, a first conductor and asecond conductor over the semiconductor, a first insulator over thefirst conductor and the second conductor, a second insulator over thesemiconductor, a third insulator over the second insulator, a thirdconductor over the third insulator, and a fourth conductor over thefirst insulator and the third conductor. The third insulator is incontact with a side surface of the first insulator. The semiconductorincludes a first region where the semiconductor overlaps with a bottomsurface of the first conductor, a second region where the semiconductoroverlaps with a bottom surface of the second conductor, and a thirdregion where the semiconductor overlaps with a bottom surface of thethird conductor. The length between a top surface of the semiconductorand the bottom surface of the third conductor is longer than the lengthbetween the first region and the third region. The length between thefourth conductor and the first conductor or the second conductor islonger than the length between the first region and the second region.

One embodiment of the present invention is a semiconductor deviceincluding a semiconductor over a substrate, a first conductor and asecond conductor over the semiconductor, a first insulator over thefirst conductor and the second conductor, a second insulator over thesemiconductor, a third insulator over the second insulator, a fourthinsulator over the third insulator, and a third conductor over thefourth insulator. The fourth insulator is in contact with a side surfaceof the first insulator. The semiconductor includes a first region wherethe semiconductor overlaps with a bottom surface of the first conductor,a second region where the semiconductor overlaps with a bottom surfaceof the second conductor, and a third region where the semiconductoroverlaps with a bottom surface of the third conductor. The lengthbetween a top surface of the semiconductor and the bottom surface of thethird conductor is longer than the length between the first region andthe third region.

One embodiment of the present invention is a semiconductor deviceincluding a semiconductor over a substrate, a first conductor and asecond conductor over the substrate, a first insulator over the firstconductor and the second conductor, a second insulator over thesemiconductor, a third insulator over the second insulator, a fourthinsulator over the third insulator, a third conductor over the fourthinsulator, and a fourth conductor over the first insulator and the thirdconductor. The fourth insulator is in contact with a side surface of thefirst insulator. The semiconductor includes a first region where thesemiconductor overlaps with a bottom surface of the first conductor, asecond region where the semiconductor overlaps with a bottom surface ofthe second conductor, and a third region where the semiconductoroverlaps with a bottom surface of the third conductor. The lengthbetween a top surface of the semiconductor and the bottom surface of thethird conductor is longer than the length between the first region andthe third region. The length between the fourth conductor and the firstconductor or the second conductor is longer than the length betweenfirst region and the second region.

In one embodiment of the present invention, the length between thefourth conductor and the first conductor or the second conductor is 1.5times or more and 2 times or less the length between the first regionand the second region.

A miniaturized transistor can be provided. A transistor with lowparasitic capacitance can be provided. A transistor with high frequencycharacteristics can be provided. A transistor with favorable electricalcharacteristics can be provided. A transistor with stable electricalcharacteristics can be provided. A transistor with low off-state currentcan be provided. A novel transistor can be provided. A semiconductordevice including the transistor can be provided. A semiconductor devicewhich can operate at high speed can be provided. A novel semiconductordevice can be provided. A module including the semiconductor device canbe provided. Furthermore, an electronic device including thesemiconductor device or the module can be provided.

Note that the description of these effects does not disturb theexistence of other effects. One embodiment of the present invention doesnot necessarily achieve all the effects listed above. Other effects willbe apparent from and can be derived from the description of thespecification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1C are a top view and cross-sectional views which illustratea transistor of one embodiment of the present invention.

FIGS. 2A to 2C are a top view and cross-sectional views which illustratea transistor of one embodiment of the present invention.

FIGS. 3A to 3C are a top view and cross-sectional views which illustratea transistor of one embodiment of the present invention.

FIGS. 4A to 4C are a top view and cross-sectional views which illustratea transistor of one embodiment of the present invention.

FIGS. 5A to 5C are a top view and cross-sectional views which illustratea transistor of one embodiment of the present invention.

FIGS. 6A to 6C are a top view and cross-sectional views which illustratea transistor of one embodiment of the present invention.

FIGS. 7A to 7H are cross-sectional views each illustrating part of atransistor of one embodiment of the present invention.

FIGS. 8A to 8F are cross-sectional views each illustrating part of atransistor of one embodiment of the present invention.

FIGS. 9A to 9D are cross-sectional views each illustrating part of atransistor of one embodiment of the present invention.

FIGS. 10A to 10C are a top view and cross-sectional views whichillustrate a transistor of one embodiment of the present invention.

FIGS. 11A and 11B are cross-sectional views illustrating transistors ofembodiments of the present invention.

FIGS. 12A to 12C are a top view and cross-sectional views illustrating atransistor of one embodiment of the present invention.

FIGS. 13A and 13B are cross-sectional views illustrating transistors ofembodiments of the present invention.

FIGS. 14A to 14C are a top view and cross-sectional views illustrating atransistor of one embodiment of the present invention.

FIGS. 15A to 15C are a top view and a cross-sectional view whichillustrate a transistor of one embodiment of the present invention.

FIGS. 16A to 16C are a top view and cross-sectional views illustrating atransistor of one embodiment of the present invention.

FIGS. 17A to 17C are a top view and cross-sectional views whichillustrate a transistor of one embodiment of the present invention.

FIGS. 18A to 18H are cross-sectional views each illustrating part of atransistor of one embodiment of the present invention.

FIGS. 19A to 19F are cross-sectional views each illustrating part of atransistor of one embodiment of the present invention.

FIGS. 20A to 20F are cross-sectional views each illustrating part of atransistor of one embodiment of the present invention.

FIG. 21 is a cross-sectional view illustrating part of a sputteringapparatus.

FIG. 22 is a cross-sectional view illustrating part of a sputteringapparatus.

FIG. 23 is a top view illustrating an example of a deposition apparatus.

FIGS. 24A to 24C illustrate a structure example of a depositionapparatus.

FIG. 25 is a top view illustrating a manufacturing apparatus of oneembodiment of the present invention.

FIG. 26 is a top view illustrating a chamber of one embodiment of thepresent invention.

FIG. 27 is a top view illustrating a chamber of one embodiment of thepresent invention.

FIGS. 28A to 28D are Cs-corrected high-resolution TEM images of a crosssection of a CAAC-OS and a cross-sectional schematic view of theCAAC-OS.

FIGS. 29A to 29D are Cs-corrected high-resolution TEM images of a planeof a CAAC-OS.

FIGS. 30A to 30C show structural analysis of a CAAC-OS and a singlecrystal oxide semiconductor by XRD.

FIGS. 31A and 31B show electron diffraction patterns of a CAAC-OS.

FIG. 32 shows a change of crystal parts of an In-Ga—Zn oxide owing toelectron irradiation.

FIGS. 33A and 33B are circuit diagrams of a semiconductor device of oneembodiment of the present invention.

FIG. 34 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention.

FIG. 35 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention.

FIG. 36 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention.

FIGS. 37A and 37B are circuit diagrams illustrating a memory device ofone embodiment of the present invention.

FIG. 38 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention.

FIG. 39 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention.

FIG. 40 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention.

FIG. 41 is a circuit diagram of a semiconductor device of one embodimentof the present invention.

FIG. 42 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention.

FIGS. 43A to 43E are circuit diagrams of a semiconductor device of oneembodiment of the present invention.

FIGS. 44A and 44B are top views each illustrating a semiconductor deviceof one embodiment of the present invention.

FIGS. 45A and 45B are block diagrams each illustrating a semiconductordevice of one embodiment of the present invention.

FIGS. 46A and 46B are each a cross-sectional view illustrating asemiconductor device of one embodiment of the present invention.

FIGS. 47A and 47B are cross-sectional views illustrating a semiconductordevice of one embodiment of the present invention.

FIGS. 48A1, 48A2, 48A3, 48B1, 48B2, and 48B3 are perspective views andcross-sectional views of a semiconductor device of one embodiment of thepresent invention.

FIG. 49 is a block diagram illustrating a semiconductor device of oneembodiment of the present invention.

FIG. 50 is a circuit diagram of a semiconductor device according to oneembodiment of the present invention.

FIGS. 51A to 51C are a circuit diagram, a top view, and across-sectional view illustrating a semiconductor device of oneembodiment of the present invention.

FIGS. 52A and 52B are a circuit diagram and a cross-sectional viewillustrating a semiconductor device of one embodiment of the presentinvention.

FIGS. 53A to 53F are perspective views each illustrating an electronicdevice of one embodiment of the present invention.

FIGS. 54A and 54B are images of the states of surfaces of samples of oneembodiment of Example 1.

FIGS. 55A to 55D are bright-field images of samples of one embodiment ofExample 2, which are taken with a scanning transmission electronmicroscope.

FIGS. 56A to 56C are a top view and cross-sectional views whichillustrate a transistor of one embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with the reference to the drawings. However, the presentinvention is not limited to the description below, and it is easilyunderstood by those skilled in the art that embodiments and detailsdisclosed herein can be modified in various ways. Further, the presentinvention is not construed as being limited to description of theembodiments. In describing structures of the present invention withreference to the drawings, common reference numerals are used for thesame portions in different drawings. Note that the same hatched patternis applied to similar parts, and the similar parts are not especiallydenoted by reference numerals in some cases.

Note that the size, the thickness of films (layers), or the region indrawings is sometimes exaggerated for simplicity.

In this specification, for example, for describing the shape of anobject, the length of one side of a minimal cube where the object fits,or an equivalent circle diameter of a cross section of the object can beinterpreted as the “diameter”, “grain size (diameter)”, “dimension”,“size”, or “width” of the object. The term “equivalent circle diameterof a cross section of the object” refers to the diameter of a perfectcircle having the same area as the cross section of the object.

Note that a voltage refers to a potential difference between a certainpotential and a reference potential (e.g., a ground potential (GND) or asource potential) in many cases. A voltage can be referred to as apotential and vice versa.

Note that the ordinal numbers such as “first” and “second” in thisspecification are used for convenience and do not denote the order ofsteps or the stacking order of layers. Therefore, for example, the term“first” can be replaced with the term “second”, “third”, or the like asappropriate. In addition, the ordinal numbers in this specification andthe like are not necessarily the same as those which specify oneembodiment of the present invention.

Note that an impurity in a semiconductor refers to, for example,elements other than the main components of the semiconductor. Forexample, an element with a concentration of lower than 0.1 atomic % isan impurity. When an impurity is contained, the density of states (DOS)may be formed in a semiconductor, the carrier mobility may be decreased,or the crystallinity may be decreased, for example. In the case wherethe semiconductor is an oxide semiconductor, examples of an impuritywhich changes characteristics of the semiconductor include Group 1elements, Group 2 elements, Group 13 elements, Group 14 elements, Group15 elements, and transition metals other than the main components;specifically, there are hydrogen (included in water), lithium, sodium,silicon, boron, phosphorus, carbon, and nitrogen, for example. In thecase of an oxide semiconductor, oxygen vacancy may be formed by entry ofimpurities such as hydrogen. Further, in the case where thesemiconductor is a silicon, examples of an impurity which changescharacteristics of the semiconductor include oxygen, Group 1 elementsexcept hydrogen, Group 2 elements, Group 13 elements, and Group 15elements.

Note that the channel length refers to, for example, a distance betweena source (a source region or a source electrode) and a drain (a drainregion or a drain electrode) in a region where a semiconductor (or aportion where a current flows in a semiconductor when a transistor ison) and a gate electrode overlap with each other or a region where achannel is formed in a top view of the transistor. In one transistor,channel lengths in all regions are not necessarily the same. In otherwords, the channel length of one transistor is not limited to one valuein some cases. Therefore, in this specification, the channel length isany one of values, the maximum value, the minimum value, or the averagevalue in a region where a channel is formed.

The channel width refers to, for example, the length of a portion wherea source and a drain face each other in a region where a semiconductor(or a portion where a current flows in a semiconductor when a transistoris on) and a gate electrode overlap with each other, or a region where achannel is formed. In one transistor, channel widths in all regions donot necessarily have the same value. In other words, a channel width ofone transistor is not fixed to one value in some cases. Therefore, inthis specification, a channel width is any one of values, the maximumvalue, the minimum value, or the average value in a region where achannel is formed.

Note that depending on transistor structures, a channel width in aregion where a channel is formed actually (hereinafter referred to as aneffective channel width) is different from a channel width shown in atop view of a transistor (hereinafter referred to as an apparent channelwidth) in some cases. For example, in a transistor having athree-dimensional structure, an effective channel width is greater thanan apparent channel width shown in a top view of the transistor, and itsinfluence cannot be ignored in some cases. For example, in aminiaturized transistor having a three-dimensional structure, theproportion of a channel region formed in a side surface of asemiconductor is increased in some cases. In that case, an effectivechannel width obtained when a channel is actually formed is greater thanan apparent channel width shown in the top view.

In a transistor having a three-dimensional structure, an effectivechannel width is difficult to measure in some cases. For example, toestimate an effective channel width from a design value, it is necessaryto assume that the shape of a semiconductor is known as an assumptioncondition. Therefore, in the case where the shape of a semiconductor isnot known accurately, it is difficult to measure an effective channelwidth accurately.

Therefore, in this specification, in a top view of a transistor, anapparent channel width that is a length of a portion where a source anda drain face each other in a region where a semiconductor and a gateelectrode overlap with each other is referred to as a surrounded channelwidth (SCW) in some cases. Further, in this specification, in the casewhere the term “channel width” is simply used, it may denote asurrounded channel width and an apparent channel width. Alternatively,in this specification, in the case where the term “channel width” issimply used, it may denote an effective channel width in some cases.Note that the values of a channel length, a channel width, an effectivechannel width, an apparent channel width, a surrounded channel width,and the like can be determined by obtaining and analyzing across-sectional TEM image and the like.

Note that in the case where electric field mobility, a current value perchannel width, and the like of a transistor are obtained by calculation,a surrounded channel width may be used for the calculation. In thatcase, a value different from one in the case where an effective channelwidth is used for the calculation is obtained in some cases.

Note that in this specification, the description “A has a shape suchthat an end portion extends beyond an end portion of B” may indicate,for example, the case where at least one of end portions of A ispositioned on an outer side than at least one of end portions of B in atop view or a cross-sectional view. Thus, the description “A has a shapesuch that an end portion extends beyond an end portion of B” can be readas the description “one end portion of A is positioned on an outer sidethan one end portion of B in a top view,” for example.

In this specification, the term “parallel” indicates that the angleformed between two straight lines is greater than or equal to −10° andless than or equal to 10°, and accordingly also includes the case wherethe angle is greater than or equal to −5° and less than or equal to 5°.The term “perpendicular” indicates that the angle formed between twostraight lines is greater than or equal to 80° and less than or equal to100°, and accordingly includes the case where the angle is greater thanor equal to 85° and less than or equal to 95°.

In this specification, the trigonal and rhombohedral crystal systems areincluded in the hexagonal crystal system.

In this specification, a term “semiconductor” can be referred to as an“oxide semiconductor”. As the semiconductor, a Group 14 semiconductorsuch as silicon or germanium; a compound semiconductor such as siliconcarbide, germanium silicide, gallium arsenide, indium phosphide, zincselenide, or cadmium sulfide; a carbon nanotube; graphene; or an organicsemiconductor can be used.

Note that in this specification and the like, a “silicon oxynitridefilm” refers to a film that includes oxygen at a higher proportion thannitrogen, and a “silicon nitride oxide film” refers to a film thatincludes nitrogen at a higher proportion than oxygen.

Note that in the case where at least one specific example is describedin a diagram or text described in one embodiment in this specificationand the like, it will be readily appreciated by those skilled in the artthat a broader concept of the specific example can be derived.Therefore, in the diagram or the text described in one embodiment, inthe case where at least one specific example is described, a broaderconcept of the specific example is disclosed as one embodiment of theinvention, and one embodiment of the invention can be constituted. Theembodiment of the present invention is clear.

Note that in this specification and the like, a content described in atleast a diagram (or may be part of the diagram) is disclosed as oneembodiment of the invention, and one embodiment of the invention can beconstituted. Therefore, when a certain content is described in adiagram, the content is disclosed as one embodiment of the inventioneven when the content is not described with a text, and one embodimentof the invention can be constituted. In a similar manner, part of adiagram, which is taken out from the diagram, is disclosed as oneembodiment of the invention, and one embodiment of the invention can beconstituted. The embodiment of the present invention is clear.

In addition, contents that are not specified in any text or drawing inthe specification can be excluded from one embodiment of the invention.Alternatively, when the range of a value that is defined by the maximumand minimum values is described, part of the range is appropriatelynarrowed or part of the range is removed, whereby one embodiment of theinvention excluding part of the range can be constituted. In thismanner, it is possible to specify the technical scope of one embodimentof the present invention so that a conventional technology is excluded,for example.

Embodiment 1 <Transistor Structure 1>

A structure of a transistor included in a semiconductor device of oneembodiment of the present invention is described below.

FIGS. 1A to 1C are a top view and cross-sectional views of thesemiconductor device of one embodiment of the present invention. FIG. 1Ais the top view. FIG. 1B is a cross-sectional view taken alongdashed-dotted line A1-A2 in FIG. 1A, which illustrates a cross-sectionalshape in the channel length direction. FIG. 1C is a cross-sectional viewtaken along dashed-dotted line A3-A4 in FIG. 1A, which illustrates across-sectional shape in the channel width direction. Note that forsimplification of the drawing, some components in the top view in FIG.1A are not illustrated.

A transistor illustrated in FIGS. 1A to 1C includes a conductor 413 andan insulator 401 over a substrate 400, an insulator 402 over theconductor 413 and the insulator 401, an insulator 406 a over theinsulator 402, a semiconductor 406 b over the insulator 406 a, aconductor 416 a and a conductor 416 b each including a region in contactwith a top surface of the semiconductor 406 b, an insulator 410 incontact with top surfaces of the insulator 402, the conductor 416 a andthe conductor 416 b and has an opening, an insulator 406 c in contactwith a side surface of the conductor 416 a and top and side surfaces ofthe semiconductor 406 b, an insulator 412 in contact with a top surfaceof the insulator 406 c and a side surface of the opening in theinsulator 410, and a conductor 404 including a conductor 404 a and aconductor 404 b, that is positioned over the semiconductor 406 b withthe insulator 412 and the insulator 406 c positioned therebetween. Notethat the conductor 404 b faces the side surface of the opening in theinsulator 410 with the conductor 404 a and the insulator 412 positionedtherebetween. A conductor 420 over the conductors 404 a and 404 b and aninsulator 408 over the insulator 412 and the conductor 420 are providedover a transistor. Alternatively, the conductor 413 and the insulator401 are not necessarily provided, and a structure without the conductor413 and the insulator 401 as illustrated in FIGS. 56A to 56C may also beused.

The insulator 406 c preferably contains at least one element containedin the semiconductor 406 b other than oxygen. This can reduce generationof defects at the interface between the semiconductor 406 b and theinsulator 406 c. Furthermore, the crystallinity of the insulator 406 ccan be improved.

It is preferable that the semiconductor 406 b and the insulator 406 ceach include a CAAC-OS which will be described later. Furthermore, theinsulator 406 a preferably includes a CAAC-OS.

In the transistor, the conductors 404 a and 404 b serve as a first gateelectrode. At least one of the conductors 404 a and 404 b is preferablya conductor that is less likely to transmit oxygen. For example, aconductor that is less likely to transmit oxygen is formed as theconductor 404 a that is a lower layer, in which case a reduction inconductivity caused by oxidization of the conductor 404 b can beprevented. In addition, the insulator 412 serves as a first gateinsulator.

The conductor 413 serves as a second gate electrode. The conductor 413can have a stacked-layer structure including a conductor that is lesslikely to transmit oxygen. The stacked-layer structure including aconductor that is less likely to transmit oxygen can prevent a reductionin conductivity due to oxidation of the conductor 413. The insulator 402serves as a second gate insulator. The potential applied to theconductor 413 can control the threshold voltage of the transistor. Whenthe first gate electrode is electrically connected to the second gateelectrode, the current in a conducting state (on-state current) can beincreased. Note that the function of the first gate electrode and thatof the second gate electrode may be interchanged.

The conductor 416 a and the conductor 416 b serve as a source electrodeand a drain electrode. Note that conductivity of the conductor can bemeasured by a two-terminal method or the like.

Therefore, the resistance of the semiconductor 406 b can be controlledby a potential applied to the conductor 404. That is, conduction ornon-conduction between the conductors 416 a and 416 b can be controlledby the potential applied to the conductor 404.

As illustrated in FIG. 1B, the top surface of the semiconductor 406 b isin contact with the conductors 416 a and 416 b. In addition, thesemiconductor 406 b can be electrically surrounded by an electric fieldof the conductor 404 serving as the gate electrode. A structure in whicha semiconductor is electrically surrounded by an electric field of agate electrode is referred to as a surrounded channel (s-channel)structure. Thus, in some cases, a channel is formed in the entiresemiconductor 406 b. In the s-channel structure, a large amount ofcurrent can flow between a source and a drain of the transistor, so thatan on-state current can be increased. In addition, since thesemiconductor 406 b is surrounded by the electric field of the conductor404, an off-state current can be decreased.

The transistor in this embodiment can also be referred to as atrench-gate self-aligned s-channel FET (TGSA s-channel FET) because theregion serving as a gate electrode is formed in a self-aligned manner tofill the opening formed in the insulator 410 and the like.

Here, in FIG. 1B, the length between a top surface of a region of thesemiconductor 406 b overlapping with the conductor 404 and a bottomsurface of the conductor 404 is denoted as t1. In FIG. 1B, the lengthbetween a region of the semiconductor 406 b overlapping with a bottomsurface of the conductor 416 a and a region of the semiconductor 406 boverlapping with the bottom surface of the conductor 404 is denoted asL1. Alternatively, the length between a region of the semiconductor 406b overlapping with a bottom surface of the conductor 416 b and theregion of the semiconductor 406 b overlapping with the bottom surface ofthe conductor 404 is denoted as L1.

In the transistor, a region having L1 is formed between a region where achannel is formed in the semiconductor 406 b (a region where theconductor 404 and the semiconductor 406 b overlap with each other) and asource region or a drain region (a region where the conductor 416 a orthe conductor 416 b overlaps with the semiconductor 406 b). The regionhaving L1 can reduce the off-state current of the transistor; however,the region with a too large L1 can reduce the on-state current of thetransistor.

The region where a channel is formed in the semiconductor 406 b iscovered with the insulator 406 c, whereby the insulator 406 c can blockentry of elements other than oxygen (such as hydrogen and silicon)included in the adjacent insulator into the region where a channel isformed. Therefore, the insulator 406 c may be formed at least over thesemiconductor 406 b.

L1 can be reduced by providing no insulator 406 c on a side surface ofthe conductor 404 with the insulator 412 positioned therebetween or byforming the insulator 406 c thinner in a region covering the sidesurface of the conductor 404 with the insulator 412 positionedtherebetween than in a region overlapping with the bottom surface of theconductor 404 with the insulator 412 positioned therebetween.Accordingly, t1 is greater than L1, and L1/t1 is less than 1.

In FIG. 1B, the length between the conductor 416 a or the conductor 416b and the conductor 420 is denoted as t2. In addition, in FIG. 1B, thelength between the conductor 416 a and the conductor 416 b is denoted asL2.

As the transistor is miniaturized, the parasitic capacitance in thevicinity of the transistor is a non-negligible and significant problem.For example, parasitic capacitance is in some cases formed between theconductor 420 and the conductor 416 a or the conductor 416 b. When thereis a large parasitic capacitance in the vicinity of the region where achannel is formed, for example, the transistor operation needs a timefor charging the parasitic capacitance, resulting in decreasing not onlythe responsiveness of the transistor but the responsiveness of thesemiconductor device. Furthermore, extra power consumption for chargingthe parasitic capacitance increases power consumption of a circuitincluding a plurality of transistors. Therefore, t2 is preferablysufficiently large such that the parasitic capacitance is negligiblysmall as compared to the gate capacitance.

L2 is reduced as the transistor is miniaturized, which leads todifficulty in applying a sufficiently large voltage to the conductor 404a and the conductor 404 b. However, when t2 has a sufficient length, theresistance of the conductor 404 a and that of the conductor 404 b can bereduced. Therefore, t2 is at least greater than L2, and t2/L2 ispreferably greater than or equal to 1.5 and less than or equal to 2.

As the substrate 400, an insulator substrate, a semiconductor substrate,or a conductor substrate may be used, for example. As the insulatorsubstrate, a glass substrate, a quartz substrate, a sapphire substrate,a stabilized zirconia substrate (e.g., an yttria-stabilized zirconiasubstrate), or a resin substrate is used, for example. As thesemiconductor substrate, a single material semiconductor substrate ofsilicon, germanium, or the like or a compound semiconductor substrate ofsilicon carbide, silicon germanium, gallium arsenide, indium phosphide,zinc oxide, gallium oxide, or the like is used, for example. Asemiconductor substrate in which an insulator region is provided in theabove semiconductor substrate, e.g., a silicon on insulator (SOI)substrate or the like is used. As the conductor substrate, a graphitesubstrate, a metal substrate, an alloy substrate, a conductive resinsubstrate, or the like is used. A substrate including a metal nitride, asubstrate including a metal oxide, or the like is used. An insulatorsubstrate provided with a conductor or a semiconductor, a semiconductorsubstrate provided with a conductor or an insulator, a conductorsubstrate provided with a semiconductor or an insulator, or the like isused. Alternatively, any of these substrates over which an element isprovided may be used. As the element provided over the substrate, acapacitor, a resistor, a switching element, a light-emitting element, amemory element, or the like is used.

Alternatively, a flexible substrate may be used as the substrate 400. Asa method for providing a transistor over a flexible substrate, there isa method in which the transistor is formed over a non-flexible substrateand then the transistor is separated and transferred to the substrate400 which is a flexible substrate. In that case, a separation layer ispreferably provided between the non-flexible substrate and thetransistor. As the substrate 400, a sheet, a film, or a foil containinga fiber may be used. The substrate 400 may have elasticity. Thesubstrate 400 may have a property of returning to its original shapewhen bending or pulling is stopped. Alternatively, the substrate 400 mayhave a property of not returning to its original shape. The substrate400 has a region with a thickness of, for example, greater than or equalto 5 μm and less than or equal to 700 μm, preferably greater than orequal to 10 μm and less than or equal to 500 μm, more preferably greaterthan or equal to 15 μm and less than or equal to 300 μm. When thesubstrate 400 has a small thickness, the weight of the semiconductordevice including the transistor can be reduced. When the substrate 400has a small thickness, even in the case of using glass or the like, thesubstrate 400 may have elasticity or a property of returning to itsoriginal shape when bending or pulling is stopped. Therefore, an impactapplied to the semiconductor device over the substrate 400, which iscaused by dropping or the like, can be reduced. That is, a durablesemiconductor device can be provided.

For the substrate 400 which is a flexible substrate, metal, an alloy,resin, glass, or fiber thereof can be used, for example. The flexiblesubstrate 400 preferably has a lower coefficient of linear expansionbecause deformation due to an environment is suppressed. The flexiblesubstrate 400 is formed using, for example, a material whose coefficientof linear expansion is lower than or equal to 1×10⁻³/K, lower than orequal to 5×10⁻⁵/K, or lower than or equal to 1×10⁻⁵/K. Examples of theresin include polyester, polyolefin, polyamide (e.g., nylon or aramid),polyimide, polycarbonate, and acrylic. In particular, aramid ispreferably used for the flexible substrate 400 because of its lowcoefficient of linear expansion.

Note that electrical characteristics of the transistor can be stabilizedwhen the transistor is surrounded by an insulator with a function ofblocking oxygen and impurities such as hydrogen. For example, aninsulator with a function of blocking oxygen and impurities such ashydrogen may be used as the insulator 408.

An insulator with a function of blocking oxygen and impurities such ashydrogen may have a single-layer structure or a stacked-layer structureincluding an insulator containing, for example, boron, carbon, nitrogen,oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine,argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium,hafnium, or tantalum may be used.

For example, the insulator 408 may be formed of aluminum oxide,magnesium oxide, silicon nitride oxide, silicon nitride, gallium oxide,germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, or tantalum oxide. Note that theinsulator 408 preferably contains aluminum oxide. For example, when theinsulator 408 is formed using plasma containing oxygen, oxygen can beadded to the insulator 410 to be a base layer of the insulator 408 or aside surface of the insulator 412. The added oxygen becomes excessoxygen in the insulator 410 or the insulator 412. When the insulator 408contains aluminum oxide, entry of impurities such as hydrogen into thesemiconductor 406 b can be inhibited. In addition, when the insulator408 contains aluminum oxide, outward diffusion of excess oxygen that isadded to the insulator 410 and the insulator 412 can be reduced, forexample.

The insulator 402 may be formed to have, for example, a single-layerstructure or a stacked-layer structure including an insulator containingboron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum. For example, the insulator402 preferably contains silicon oxide or silicon oxynitride.

Note that the insulator 410 preferably includes an insulator with lowrelative dielectric constant. For example, the insulator 410 preferablycontains silicon oxide, silicon oxynitride, silicon nitride oxide,silicon nitride, silicon oxide to which fluorine is added, silicon oxideto which carbon is added, silicon oxide to which carbon and nitrogen areadded, silicon oxide having pores, a resin, or the like. Alternatively,the insulator 410 preferably has a stacked-layer structure of a resinand one of the following materials: silicon oxide, silicon oxynitride,silicon nitride oxide, silicon nitride, silicon oxide to which fluorineis added, silicon oxide to which carbon is added, silicon oxide to whichcarbon and nitrogen are added, and silicon oxide having pores. Whensilicon oxide or silicon oxynitride, which is thermally stable, iscombined with a resin, the stacked-layer structure can have thermalstability and low relative dielectric constant. Examples of the resininclude polyester, polyolefin, polyamide (e.g., nylon or aramid),polyimide, polycarbonate, and acrylic.

The insulator 412 may be formed to have, for example, a single-layerstructure or a stacked-layer structure including an insulator containingboron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum. For example, for theinsulator 412, a material containing silicon oxide or silicon oxynitrideis preferably used.

Note that the insulator 412 preferably contains an insulator with a highdielectric constant. For example, the insulator 412 preferably includesgallium oxide, hafnium oxide, oxide including aluminum and hafnium,oxynitride including aluminum and hafnium, oxide including silicon andhafnium, oxynitride including silicon and hafnium, or the like. Theinsulator 412 preferably has a stacked-layer structure including siliconoxide or silicon oxynitride and an insulator with a high dielectricconstant. Because silicon oxide and silicon oxynitride have thermalstability, combination of silicon oxide or silicon oxynitride with aninsulator with a high dielectric constant allows the stacked-layerstructure to be thermally stable and have a high dielectric constant.For example, when an aluminum oxide, a gallium oxide, or a hafnium oxideof the insulator 412 is on the insulator 406 c side, entry of siliconincluded in the silicon oxide or the silicon oxynitride into thesemiconductor 406 b can be suppressed. When silicon oxide or siliconoxynitride is on the insulator 406 c side, for example, trap centersmight be formed at the interface between aluminum oxide, gallium oxide,or hafnium oxide and silicon oxide or silicon oxynitride. The trapcenters can shift the threshold voltage of the transistor in thepositive direction by trapping electrons in some cases.

Each of the conductors 416 a and 416 a may be formed to have asingle-layer structure or a stacked-layer structure including aconductor containing, for example, one or more kinds of boron, nitrogen,oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium,manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium,molybdenum, ruthenium, platinum, silver, indium, tin, tantalum, andtungsten. For example, an alloy film or a compound film may be used: aconductor containing aluminum, a conductor containing copper andtitanium, a conductor containing copper and manganese, a conductorcontaining indium, tin, and oxygen, a conductor containing titanium andnitrogen, or the like may be used.

Each of the conductors 404, 413, and 420 may be formed to have asingle-layer structure or a stacked-layer structure including aconductor containing, for example, one or more kinds of boron, nitrogen,oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium,manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium,molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. Forexample, an alloy film or a compound film may be used: a conductorcontaining aluminum, a conductor containing copper and titanium, aconductor containing copper and manganese, a conductor containingindium, tin, and oxygen, a conductor containing titanium and nitrogen,or the like may be used.

An oxide semiconductor is preferably used as the semiconductor 406 b.However, silicon (including strained silicon), germanium, silicongermanium, silicon carbide, gallium arsenide, aluminum gallium arsenide,indium phosphide, gallium nitride, an organic semiconductor, or the likecan be used in some cases.

As the insulator 406 a and the insulator 406 c, oxides containing one ormore elements other than oxygen contained in the semiconductor 406 b arepreferably used. However, silicon (including strained silicon),germanium, silicon germanium, silicon carbide, gallium arsenide,aluminum gallium arsenide, indium phosphide, gallium nitride, an organicsemiconductor, or the like can be used in some cases.

The semiconductor 406 b is an oxide semiconductor, for example. Thesemiconductor 406 b can have high carrier mobility (electron mobility)by containing indium, for example. The semiconductor 406 b preferablycontains an element M. The element M is preferably aluminum, gallium,yttrium, tin, or the like. Other elements which can be used as theelement M are boron, silicon, titanium, iron, nickel, germanium,zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum,tungsten, magnesium, and the like. Note that two or more of the aboveelements may be used in combination as the element M. The element M isan element having high bonding energy with oxygen, for example. Theelement M is an element whose bonding energy with oxygen is higher thanthat of indium. The element M is an element that can increase the energygap of the oxide semiconductor, for example. Furthermore, thesemiconductor 406 b preferably contains zinc. When the oxidesemiconductor contains zinc, the oxide semiconductor is easily to becrystallized, for example.

Note that the semiconductor 406 b is not limited to the oxidesemiconductor. The semiconductor 406 b may be, for example, an oxidesemiconductor which does not contain indium and contains zinc, an oxidesemiconductor which does not contain indium and contains gallium, or anoxide semiconductor which does not contain indium and contains tin,e.g., a zinc tin oxide or a gallium tin oxide.

For the semiconductor 406 b, an oxide with a wide energy gap may beused. For example, the energy gap of the semiconductor 406 b is greaterthan or equal to 2.5 eV and less than or equal to 4.2 eV, preferablygreater than or equal to 2.8 eV and less than or equal to 3.8 eV, morepreferably greater than or equal to 3 eV and less than or equal to 3.5eV.

The insulator 406 a and the insulator 406 c are oxides including one ormore elements, or two or more elements other than oxygen included in thesemiconductor 406 b. Since the insulator 406 a and the insulator 406 ceach include one or more elements, or two or more elements other thanoxygen included in the semiconductor 406 b, a defect state is lesslikely to be formed at the interface between the insulator 406 a and thesemiconductor 406 b and the interface between the semiconductor 406 band the insulator 406 c.

As the semiconductor 406 b, an oxide having an electron affinity higherthan those of the insulators 406 a and 406 c is used. For example, asthe semiconductor 406 b, an oxide having an electron affinity higherthan those of the insulators 406 a and 406 c by 0.07 eV or higher and1.3 eV or lower, preferably 0.1 eV or higher and 0.7 eV or lower, orfurther preferably 0.15 eV or higher and 0.4 eV or lower is used. Notethat the electron affinity refers to an energy gap between the vacuumlevel and the bottom of the conduction band.

When gate voltage is applied to such a transistor in which the insulator406 a is placed under the semiconductor 406 b and the insulator 406 c isplaced over the semiconductor 406 b, a channel is formed in thesemiconductor 406 b whose electron affinity is the highest among theinsulator 406 a, the semiconductor 406 b, and the insulator 406 c. Inthis manner, a buried channel structure is formed.

Here, in some cases, there is a mixed region of the insulator 406 a andthe semiconductor 406 b between the insulator 406 a and thesemiconductor 406 b. Furthermore, in some cases, there is a mixed regionof the semiconductor 406 b and the insulator 406 c between thesemiconductor 406 b and the insulator 406 c. The mixed region has a lowdensity of defect states. For that reason, in a stack including theinsulator 406 a, the semiconductor 406 b, and the insulator 406 c,energy changes continuously at their interfaces and in the vicinity ofthe interface (continuous junction). Note that boundaries of theinsulator 406 a, the semiconductor 406 b, and the insulator 406 c arenot clear in some cases.

At this time, electrons move mainly in the semiconductor 406 b, not inthe insulator 406 a and the insulator 406 c.

As factors of inhibiting electron movement are decreased, the on-statecurrent of the transistor can be increased. Electron movement isinhibited, for example, in the case where physical unevenness in achannel formation region is large.

To increase the on-state current of the transistor, for example, rootmean square (RMS) roughness with a measurement area of 1 μm×1 μm of thetop surface or the bottom surface of the semiconductor 406 b (aformation surface; here, the top surface of the insulator 406 a) is lessthan 1 nm, preferably less than 0.6 nm, further preferably less than 0.5nm, still further preferably less than 0.4 nm. The average surfaceroughness (also referred to as Ra) with the measurement area of 1 μm×1μm is less than 1 nm, preferably less than 0.6 nm, further preferablyless than 0.5 nm, still further preferably less than 0.4 nm. The maximumdifference (P−V) with the measurement area of 1 μm×1 μm is less than 10nm, preferably less than 9 nm, further preferably less than 8 nm, stillfurther preferably less than 7 nm. RMS roughness, Ra, and P−V can bemeasured using a scanning probe microscope SPA-500 manufactured by SIINano Technology Inc.

The above three-layer structure is an example. For example, astacked-layer structure in which any one of the insulators described asexamples of the insulator 406 a and the insulator 406 c is providedbelow or over the insulator 406 a or below or over the insulator 406 cmay be employed.

Note that an oxide semiconductor which can be used for the semiconductorwill be described in detail in another embodiment.

<Method 1 for Manufacturing Transistor>

A method for manufacturing the transistor of the present invention inFIGS. 1A to 1C will be described below with reference to FIGS. 7A to 7H,FIGS. 8A to 8F, and FIGS. 9A to 9D.

First, the substrate 400 is prepared.

Next, as illustrated in FIGS. 7A and 7B, an insulator to be theinsulator 401 is formed over the substrate 400. An opening is formed inthe insulator 401, and a conductor to be the conductor 413 is formedover the insulator 401. The conductor to be the conductor 413 can beformed by a sputtering method, a CVD method, an MBE method, a PLDmethod, an ALD method, or the like. The conductor 413 may have amultilayer structure including a conductor that is less likely totransmit oxygen (also referred to as a conductor with high stabilityagainst oxidation). The conductor 413 may be embedded to the opening inthe insulator 401 by chemical mechanical polishing (CMP) or the like.Alternatively, the conductor 413 may be formed in such a manner that aconductor is formed and processed by a photolithography method or thelike.

In the photolithography method, first, a resist is exposed to lightthrough a photomask. Next, a region exposed to light is removed or leftusing a developing solution, so that a resist mask is formed. Then,etching through the resist mask is conducted. As a result, theconductor, the semiconductor, the insulator, or the like can beprocessed into a desired shape. The resist mask is formed by, forexample, exposure of the resist to light using KrF excimer laser light,ArF excimer laser light, extreme ultraviolet (EUV) light, or the like.Alternatively, a liquid immersion technique may be employed in which aportion between a substrate and a projection lens is filled with liquid(e.g., water) to perform light exposure. An electron beam or an ion beammay be used instead of the above-mentioned light. Note that dry etchingtreatment such as ashing or wet etching treatment can be used forremoval of the resist mask. Alternatively, wet etching treatment isperformed after dry etching treatment. Further alternatively, dryetching treatment is performed after wet etching treatment.

As a dry etching apparatus, a capacitively coupled plasma (CCP) etchingapparatus including parallel plate type electrodes can be used. Thecapacitively coupled plasma etching apparatus including the parallelplate type electrodes may have a structure in which a high-frequencypower source is applied to one of the parallel plate type electrodes.Alternatively, the capacitively coupled plasma etching apparatus mayhave a structure in which different high-frequency power sources areapplied to one of the parallel plate type electrodes. Alternatively, thecapacitively coupled plasma etching apparatus may have a structure inwhich high-frequency power sources with the same frequency are appliedto the parallel plate type electrodes. Alternatively, the capacitivelycoupled plasma etching apparatus may have a structure in whichhigh-frequency power sources with different frequencies are applied tothe parallel plate type electrodes. Alternatively, a dry etchingapparatus including a high-density plasma source can be used. As the dryetching apparatus including a high-density plasma source, an inductivelycoupled plasma (ICP) etching apparatus can be used, for example.

Next, as indicated by arrows in FIGS. 7A and 7B, high-density-plasmatreatment may be performed. High-density-plasma treatment is preferablyperformed in an oxygen atmosphere or a nitrogen atmosphere. The oxygenatmosphere is a gas atmosphere containing oxygen atoms, which includesatmospheres of oxygen, ozone, and nitrogen oxide (e.g., nitrogenmonoxide, nitrogen dioxide, dinitrogen monoxide, dinitrogen trioxide,dinitrogen tetroxide, or dinitrogen pentoxide). In the oxygenatmosphere, an inert gas such as nitrogen or a rare gas (e.g., helium orargon) may be included. When high-density plasma treatment is performedin an oxygen atmosphere in such a manner, carbon, hydrogen, or the likecan be released. In addition, in the case where high-density-plasmatreatment is performed in an oxygen atmosphere, organic compound such ashydrocarbon can be easily released from an object.

The high-density plasma treatment in a nitrogen atmosphere may behigh-density plasma treatment in an atmosphere containing nitrogen and arare gas, an atmosphere containing nitrogen, hydrogen, and a rare gas,or an atmosphere containing ammonia and a rare gas, for example. Withthis high-density plasma treatment in a nitrogen atmosphere, a surfaceof the treated object and its vicinity can be nitrided. The nitridedregion can be formed to be extremely thin on the surface side of thetreated object. This nitrided region can prevent diffusion ofimpurities.

After the high-density plasma treatment in an oxygen atmosphere isperformed, the high-density plasma treatment in a nitrogen atmospheremay be performed. Alternatively, after the high-density plasma treatmentin a nitrogen atmosphere is performed, the high-density plasma treatmentin an oxygen atmosphere may be performed. Annealing treatment may beperformed before or after each high-density plasma treatment. Note thatit is in some cases preferable to let an enough amount of gas flow inorder to increase the plasma density. When the gas amount is not enough,the deactivation rate of radicals becomes higher than the generationrate of radicals in some cases. For example, it is preferable in somecases to let a gas flow at 100 sccm or more, 300 sccm or more, or 800sccm or more.

The high-density plasma treatment is performed using a microwavegenerated with a high-frequency generator that generates a wave having afrequency of, for example, more than or equal to 0.3 GHz and less thanor equal to 3.0 GHz, more than or equal to 0.7 GHz and less than orequal to 1.1 GHz, or more than or equal to 2.2 GHz and less than orequal to 2.8 GHz (typically, 2.45 GHz). The treatment pressure can behigher than or equal to 10 Pa and lower than or equal to 5000 Pa,preferably higher than or equal to 200 Pa and lower than or equal to1500 Pa, further preferably higher than or equal to 300 Pa and lowerthan or equal to 1000 Pa. The substrate temperature can be higher thanor equal to 100° C. and lower than or equal to 600° C. (typically 400°C.). Furthermore, a mixed gas of oxygen and argon can be used.

For example, the high density plasma is generated using a 2.45 GHzmicrowave and preferably has an electron density of higher than or equalto 1×10¹¹/cm³ and lower than or equal to 1×10¹³/cm³, an electrontemperature of 2 eV or lower, or an ion energy of 5 eV or lower. Suchhigh-density plasma treatment produces radicals with low kinetic energyand causes little plasma damage, compared with conventional plasmatreatment. Thus, formation of a film with few defects is possible. Thedistance between an antenna that generates the microwave and the treatedobject is longer than or equal to 5 mm and shorter than or equal to 120mm, preferably longer than or equal to 20 mm and shorter than or equalto 60 mm.

Alternatively, a plasma power source that applies a radio frequency (RF)bias to a substrate may be provided. The frequency of the RF bias may be13.56 MHz, 27.12 MHz, or the like, for example. The use of high-densityplasma enables high-density oxygen ions to be produced, and applicationof the RF bias to the substrate allows oxygen ions generated by thehigh-density plasma to be efficiently introduced into the treatedobject. Therefore, it is preferable to perform the high-density plasmatreatment while a bias is applied to the substrate.

Following the high-density plasma treatment, annealing treatment may besuccessively performed without an exposure to the air. Followingannealing treatment, the high-density plasma treatment may besuccessively performed without an exposure to the air. By performinghigh-density plasma treatment and annealing treatment in succession,entry of impurities during the treatment can be suppressed. Moreover, byperforming annealing treatment after the high-density plasma treatmentin an oxygen atmosphere, unnecessary oxygen that is added into thetreated object but is not used to fill oxygen vacancies can beeliminated. The annealing treatment may be performed by lamp annealingor the like, for example.

The treatment time of the high-density plasma treatment is preferablylonger than or equal to 30 seconds and shorter than or equal to 120minutes, longer than or equal to 1 minute and shorter than or equal to90 minutes, longer than or equal to 2 minutes and shorter than or equalto 30 minutes, or longer than or equal to 3 minutes and shorter than orequal to 15 minutes.

The treatment time of the annealing treatment at a temperature of higherthan or equal to 250° C. and lower than or equal to 800° C., higher thanor equal to 300° C. and lower than or equal to 700° C., or higher thanor equal to 400° C. and lower than or equal to 600° C. is preferablylonger than or equal to 30 seconds and shorter than or equal to 120minutes, longer than or equal to 1 minute and shorter than or equal to90 minutes, longer than or equal to 2 minutes and shorter than or equalto 30 minutes, or longer than or equal to 3 minutes and shorter than orequal to 15 minutes.

Next, the insulator 402 is formed. The insulator 402 may be formed by asputtering method, a chemical vapor deposition (CVD) method, a molecularbeam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, anatomic layer deposition (ALD) method, or the like.

CVD methods can be classified into a plasma enhanced CVD (PECVD) methodusing plasma, a thermal CVD (TCVD) method using heat, a photo CVD methodusing light, and the like. Moreover, the CVD method can include a metalCVD (MCVD) method and a metal organic CVD (MOCVD) method depending on asource gas.

By using the PECVD method, a high-quality film can be formed at arelatively low temperature. Furthermore, a thermal CVD method does notuse plasma and thus causes less plasma damage to an object. For example,a wiring, an electrode, an element (e.g., transistor or capacitor), orthe like included in a semiconductor device might be charged up byreceiving charges from plasma. In that case, accumulated charges mightbreak the wiring, electrode, element, or the like included in thesemiconductor device. By contrast, when a thermal CVD method not usingplasma is employed, such damage due to exposure to plasma is not causedand the yield of the semiconductor device can be increased. In a thermalCVD method, an object is not exposed to plasma during deposition, sothat a film with few defects can be obtained.

An ALD method also causes less plasma damage to an object. An ALD methoddoes not cause plasma damage during deposition, so that a film with fewdefects can be obtained.

Unlike in a deposition method in which particles ejected from a targetor the like are deposited, in a CVD method and an ALD method, a film isformed by reaction at a surface of an object. Thus, a CVD method and anALD method enable favorable step coverage almost regardless of the shapeof an object. In particular, an ALD method enables excellent stepcoverage and excellent thickness uniformity and can be favorably usedfor covering a surface of an opening with a high aspect ratio, forexample. On the other hand, an ALD method has a low deposition rate;thus, it is sometimes preferable to combine an ALD method with anotherdeposition method with a high deposition rate such as a CVD method.

When a CVD method or an ALD method is used, composition of a film to beformed can be controlled with a flow rate ratio of the source gases. Forexample, by a CVD method or an ALD method, a film with a certaincomposition can be formed depending on a flow rate ratio of the sourcegases. Moreover, with a CVD method or an ALD method, by changing theflow rate ratio of the source gases while forming the film, a film whosecomposition is continuously changed can be formed. In the case where thefilm is formed while changing the flow rate ratio of the source gases,as compared to the case where the film is formed using a plurality ofdeposition chambers, time taken for the film formation can be reducedbecause time taken for transfer and pressure adjustment is omitted.Thus, semiconductor devices can be manufactured with improvedproductivity.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

In addition, treatment to add oxygen to the insulator 402 may beperformed. For the treatment to add oxygen, an ion implantation method,a plasma treatment method, or the like can be used. Note that oxygenadded to the insulator 402 is excess oxygen.

Next, as illustrated in FIGS. 7C and 7D, an insulator to be theinsulator 406 a, a semiconductor to be the semiconductor 406 b, and aresist mask 430 are formed.

First, an insulator to be the insulator 406 a is formed over theinsulator 402. The insulator to be the insulator 406 a can be formed bya sputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like. It is particularly preferable to use afacing-target sputtering apparatus. Note that in this specification andthe like, deposition using a facing-target sputtering apparatus can alsobe referred to as vapor deposition sputtering (VDSP).

The use of the facing-target sputtering apparatus can reduce plasmadamage induced during deposition of the insulator. Thus, oxygenvacancies in the insulator can be reduced. In addition, the use of thefacing-target sputtering apparatus allows deposition in high vacuum. Inthat case, impurity concentration (e.g., concentration of hydrogen, arare gas (such as argon), or water) in the deposited insulator can bereduced.

Alternatively, a sputtering apparatus including an inductively-coupledantenna conductor plate may be used. Thus, a large film with highuniformity can be formed with a high deposition rate.

Deposition is preferably performed using a gas containing oxygen, a raregas, a gas containing nitrogen, or the like. As the gas containingnitrogen, nitrogen (N₂), dinitrogen oxide (N₂O), ammonia (NH₃), or thelike may be used, for example.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

In addition, treatment to add oxygen to the insulator to be theinsulator 406 a may be performed. For the treatment to add oxygen, anion implantation method, a plasma treatment method, or the like can beused. Note that oxygen added to the insulator to be the insulator 406 ais excess oxygen.

Next, the semiconductor to be the semiconductor 406 b is formed over theinsulator to be the insulator 406 a. The semiconductor can be formed bya sputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like. It is particularly preferable to use afacing-target sputtering apparatus.

The use of the facing-target sputtering apparatus can reduce plasmadamage induced during deposition of the semiconductor. Accordingly,oxygen vacancies in the semiconductor can be reduced. In addition, theuse of the facing-target sputtering apparatus allows deposition in highvacuum. In that case, impurity concentration (e.g., concentration ofhydrogen, a rare gas (such as argon), or water) in the depositedsemiconductor can be reduced.

Alternatively, a sputtering apparatus including an inductively-coupledantenna conductor plate may be used. Thus, a large film with highuniformity can be formed with a high deposition rate.

Deposition is preferably performed using a gas containing oxygen, a raregas, a gas containing nitrogen, or the like. As the gas containingnitrogen, nitrogen (N₂), dinitrogen oxide (N₂O), or ammonia (NH₃) may beused, for example.

Next, first heat treatment is preferably performed. The first heattreatment can be performed at a temperature higher than or equal to 250°C. and lower than or equal to 650° C., preferably higher than or equalto 450° C. and lower than or equal to 600° C. The first heat treatmentis performed in an inert gas atmosphere or an atmosphere containing anoxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The firstheat treatment may be performed under a reduced pressure. Alternatively,the first heat treatment may be performed in such a manner that heattreatment is performed in an inert gas atmosphere, and then another heattreatment is performed in an atmosphere containing an oxidizing gas at10 ppm or more, 1% or more, or 10% or more in order to compensatedesorbed oxygen. By the first heat treatment, crystallinity of thesemiconductor can be increased and impurities such as hydrogen andmoisture can be removed, for example. Alternatively, in the first heattreatment, plasma treatment using oxygen may be performed under areduced pressure. The plasma treatment containing oxygen is preferablyperformed using an apparatus including a power source for generatinghigh-density plasma using microwaves, for example. Alternatively, aplasma power source for applying a radio frequency (RF) voltage to asubstrate side may be provided. The use of high-density plasma enableshigh-density oxygen radicals to be produced, and application of the RFvoltage to the substrate side allows oxygen radicals generated by thehigh-density plasma to be efficiently introduced into the semiconductor406 b. Alternatively, after plasma treatment using an inert gas with theapparatus, plasma treatment using oxygen in order to compensate releasedoxygen may be performed.

Next, the insulator to be the insulator 406 a and the semiconductor tobe the semiconductor 406 b are processed by a photolithography method orthe like using a resist mask 430 to form a multilayer film including theinsulator 406 a and the semiconductor 406 b as illustrated in FIGS. 7Eand 7F. Note that when the multilayer film is formed, the insulator 402is also subjected etching to have a thinned region in some cases. Thatis, the insulator 402 may have a protruding portion in a region incontact with the multilayer film.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, as illustrated in FIGS. 7G and 7H, a conductor 416 and aninsulator to be the insulator 410 are formed.

First, the conductor 416 is formed. The conductor 416 can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like.

Note that the conductor 416 covers the multilayer film. The side surfaceof the insulator 406 a and the top and side surfaces of thesemiconductor 406 b are partly damaged in forming the conductor over themultilayer film, and then a region where resistance is reduced might beformed. Since each of the insulator 406 a and the semiconductor 406 bincludes a region whose resistance is lowered, the contact resistancebetween the conductor 416 and the semiconductor 406 b can be lowered.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, the conductor 416 is processed by a photolithography method or thelike, so that the conductors 416 a and 416 b are formed.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, the insulator to be the insulator 410 is formed. The insulator tobe the insulator 410 can be formed by a sputtering method, a CVD method,an MBE method, a PLD method, an ALD method, or the like. Alternatively,the insulator to be the insulator 410 can be formed by a spin coatingmethod, a dipping method, a droplet discharging method (such as anink-jet method), a printing method (such as screen printing or offsetprinting), a doctor knife method, a roll coater method, a curtain coatermethod, or the like.

The insulator to be the insulator 410 may be formed to have a flat topsurface. For example, the top surface of the insulator to be theinsulator 410 may have planarity immediately after the film formation.Alternatively, after the film formation, an upper portion of theinsulator to be the insulator 410 may be removed so that the top surfaceof the insulator to be the insulator 410 becomes parallel to a referencesurface such as a rear surface of the substrate. Such treatment isreferred to as planarization treatment. As the planarization treatment,for example, chemical mechanical polishing treatment, dry etchingtreatment, or the like can be performed. However, the top surface of theinsulator to be the insulator 410 is not necessarily flat.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, a resist mask 431 is formed over the insulator to be the insulator410 by a photolithography method or the like. Here, an organic coatingfilm may be formed between the top surface of the insulator to be theinsulator 410 and the resist mask 431 in order to improve the adhesionbetween the top surface of the insulator to be the insulator 410 and theresist mask 431.

Next, as illustrated in FIGS. 8A and 8B, an opening is formed in theinsulator 410 and the conductor 416. First, after the resist mask 431 isformed, the insulator to be the insulator 410 is subjected to a firstprocessing by a dry etching method or the like to expose the top surfaceof the conductor 416. In a dry etching method, any of the above dryetching apparatuses can be used; however, a dry etching apparatus inwhich high-frequency power sources with different frequencies areconnected to the parallel-plate electrodes is preferably used.

Next, the conductor 416 is subjected to a second processing by a dryetching method or the like so as to be separated into the conductor 416a and the conductor 416 b. Note that the insulator 410 and the conductor416 may be processed in the same photolithography process. Processing inthe same photolithography process can reduce the number of manufacturingsteps. Thus, a semiconductor device including the transistor can bemanufactured with high productivity.

At this time, the semiconductor 406 b has a region that is exposed. Theexposed region of the semiconductor 406 b is partly removed by thesecond processing in some cases. Furthermore, impurity elements such asresidual components of the etching gas are attached to the exposedsurface of the semiconductor 406 b in some cases. For example, chlorineand the like may be attached when a chlorine-based gas is used as theetching gas. When a hydrocarbon-based gas is used as the etching gas,carbon, hydrogen, and the like may be attached. The impurity elementsattached to the exposed surface of the semiconductor 406 b arepreferably reduced. The impurity elements can be reduced by cleaningtreatment using dilute hydrofluoric acid, cleaning treatment usingozone, cleaning treatment using ultra violet rays, or the like. Notethat some kinds of cleaning treatment may be used in combination.Accordingly, the exposed surface of the semiconductor 406 b, that is,the region where channel is formed has a high resistance.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, as illustrated in FIGS. 8C and 8D, the insulator 406 c is formedover top and side surfaces of the semiconductor 406 b, a side surface ofthe insulator 406 a, a top surface of the insulator 402, and a topsurface of the insulator 410, which are surfaces except for at least aside surface of the insulator 410. The insulator 406 c can be formed bya sputtering method.

Here, a sputtering apparatus which is used for formation of theinsulator 406 c is described with reference to FIG. 21 and FIG. 22.

FIG. 21 is a cross-sectional view illustrating part of a sputteringapparatus 101. The sputtering apparatus 101 illustrated in FIG. 21includes a member 190, a collimator 150 placed over the member 190, atarget holder 120, a backing plate 110 placed over the target holder120, a target 100 placed over the backing plate 110, a magnet unit 130including a magnet 130N and a magnet 130S placed under the target 100with the backing plate 110 positioned therebetween, and a magnet holder132 that supports the magnet unit 130. Note that in this specification,a magnet unit means a group of magnets. The magnet unit can be replacedwith “cathode”, “cathode magnet”, “magnetic member”, “magnetic part”, orthe like.

A substrate stage 170 placed to face the target 100 and a substrate 160held by the substrate stage 170 are illustrated. FIG. 21 alsoillustrates a magnetic force line 180 a and a magnetic force line 180 bformed by the magnet unit 130.

The target holder 120 and the backing plate 110 are fixed to each otherwith a bolt and have the same potential. The target holder 120 has afunction of supporting the target 100 with the backing plate 110positioned therebetween.

The backing plate 110 has a function of fixing the target 100.

The sputtering apparatus 101 may have a water channel inside or underthe backing plate 110. By making fluid (air, nitrogen, a rare gas,water, oil, or the like) flow through the water channel, dischargeanomaly due to an increase in the temperature of the target 100 ordamage to the sputtering apparatus 101 due to deformation of a componentsuch as the target 100 can be prevented in the sputtering. In that case,the backing plate 110 and the target 100 are preferably adhered to eachother with a bonding member because the cooling capability is increased.

A gasket is preferably provided between the target holder 120 and thebacking plate 110, in which case an impurity is less likely to enter thesputtering apparatus 101 from the outside or a water channel.

In the magnet unit 130, the magnet 130N and the magnet 130S are placedsuch that their surfaces on the target 100 side have oppositepolarities. Here, the case where the pole of the magnet 130N on thetarget 100 side is the north pole and the pole of the magnet 130S on thetarget 100 side is the south pole is described. Note that the layout ofthe magnets and the polarities in the magnet unit 130 is not limited tothose illustrated in FIG. 21.

The magnetic force line 180 a is one of magnetic force lines that form ahorizontal magnetic field in the vicinity of a top surface of the target100. The vicinity of the top surface of the target 100 corresponds to aregion in which the perpendicular distance from the top surface of thetarget 100 is, for example, greater than or equal to 0 mm and less thanor equal to 10 mm, in particular, greater than or equal to 0 mm and lessthan or equal to 5 mm.

The magnetic force line 180 b is one of magnetic force lines that form ahorizontal magnetic field in a plane apart from the top surface of themagnet unit 130 by a perpendicular distance d. The perpendiculardistance d is, for example, greater than or equal to 0 mm and less thanor equal to 20 mm or greater than or equal to 5 mm and less than orequal to 15 mm.

In the deposition, a potential V1 applied to the target holder 120 is,for example, lower than a potential V2 applied to the substrate stage170. The potential V2 applied to the substrate stage 170 is, forexample, the ground potential. A potential V3 applied to the magnetholder 132 is, for example, the ground potential. Note that thepotentials V1, V2, and V3 are not limited to the above description. Notall the target holder 120, the substrate stage 170, and the magnetholder 132 are necessarily supplied with potentials. For example, thesubstrate stage 170 may be electrically floating.

FIG. 21 illustrates an example where the backing plate 110 and thetarget holder 120 are not electrically connected to the magnet unit 130and the magnet holder 132, but electrical connection is not limitedthereto. For example, the backing plate 110 and the target holder 120may be electrically connected to the magnet unit 130 and the magnetholder 132, and the backing plate 110, the target holder 120, the magnetunit 130, and the magnet holder 132 may have the same potential.

When the potential V1 is applied to the target holder 120 under theconditions that the deposition gas (e.g., oxygen, nitrogen, or a raregas such as argon) flows in the sputtering apparatus 101 and thepressure in the sputtering apparatus 101 is constant (e.g., greater thanor equal to 0.05 Pa and less than or equal to 10 Pa, preferably greaterthan or equal to 0.1 Pa and less than or equal to 0.8 Pa), a plasma isformed in a magnetic field formed by the magnet unit 130. The potentialof the plasma is a potential Vp that is higher than the potential V1. Atthis time, a cation in the plasma is accelerated toward the target 100by a potential difference between the potential Vp and the potential V1.Then, the cation collides with the target 100 to release sputteredparticles. The released sputtered particles that reach the substrate 160are deposited to form a film.

In a sputtering apparatus in general, a sputtered particle is lesslikely to reach a bottom portion of a small opening with a high aspectratio. In addition, a sputtered particle, which flies in the obliquedirection to the substrate, is deposited in the vicinity of upper partof an opening, which narrows the width of the upper part of the opening.In that case, the sputtered particle is not formed in the opening.

In contrast, with use of the sputtering apparatus with the abovestructure, released sputtered particles that fly in the obliquedirection to the formation surface of the substrate 160 are attached tothe collimator 150. That is, sputtered particles having a perpendicularcomponent to the substrate 160, which have passed through the collimator150 provided between the target 100 and the substrate 160, reach thesubstrate. Thus, sputtered particles are deposited on a plane parallelto the substrate. On the other hand, sputtered particles are notdeposited on a plane perpendicular to the substrate, or the amount ofdeposition thereof on the plane perpendicular to the substrate issmaller than that on the plane parallel to the substrate. Therefore,with use of the sputtering apparatus with the above structure, theinsulator 406 c can be formed on planes without planes perpendicular tothe substrate as illustrated in FIGS. 8C and 8D.

The perpendicular distance between the target 100 and the collimator 150and that between the substrate 160 and the collimator 150 may beappropriately changed in accordance with quality of a film which isformed. Thus, the collimator 150 may include a movable portion 151 and amovable portion 152 as illustrated in FIG. 22. By including the movableportion 151, whether the collimator 150 is used or not can be easilyselected. By including the movable portion 152, the perpendiculardistance between the collimator 150 and the substrate 160 and thatbetween the collimator 150 and the target 100 can be easily adjusted.

Alternatively, a long throw sputtering method can also be used. In thelong throw sputtering method, the perpendicular distance between thetarget 100 and the substrate 160 is set large, whereby the incidentdirection of the sputtered particle can be approximately perpendicularto the substrate 160. Accordingly, the insulator 406 c can be formed onplanes without planes perpendicular to the substrate even when thecollimator 150 is not used. Note that the perpendicular distance betweenthe substrate 160 and the target 100 is greater than or equal to 150 mmand less than or equal to 500 mm. Note that a combination of the longthrow sputtering method and the collimator 150 may be employed.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, as illustrated in FIGS. 8E and 8F, an insulator to be theinsulator 412, a conductor to be the conductor 404 a, and a conductor tobe the conductor 404 b are formed.

First, an insulator to be the insulator 412 is formed over the insulator410 and the insulator 406 c. The insulator to be the insulator 412 canbe formed by a sputtering method, a CVD method, an MBE method, a PLDmethod, an ALD method, or the like.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, a conductor to be the conductor 404 a and a conductor to be theconductor 404 b are formed. The conductor to be the conductor 404 a andthe conductor to be the conductor 404 b can be formed by a sputteringmethod, a CVD method, an MBE method, a PLD method, an ALD method, or thelike. The conductor to be the conductor 404 a and the conductor theconductor to be the conductor 404 b are formed so as to fill the openingformed in the insulator 410 and the like. Therefore, the CVD method (theMCVD method, in particular) is preferred. A stacked-layer film of aconductor formed by an ALD method or the like and a conductor formed bya CVD method is preferred in some cases to increase adhesion of theconductor formed by an MCVD method. For example, a stacked-layer filmwhere titanium nitride and tungsten are formed in this order may beused.

Next, as illustrated in FIGS. 9A and 9B, the conductor 404 a, theconductor 404 b, the insulator 412, and the insulator 406 c are removedto expose the insulator 410 by CMP treatment or the like. Here, theinsulator 410 can be used as a stopper layer and the thickness of theinsulator 410 is reduced in some cases. Therefore, the insulator 410 isset to have a sufficient thickness so that the conductor 404 a and theconductor 404 b have sufficiently low resistance in a completedtransistor, whereby a plurality of transistors with small variation incharacteristics can be manufactured.

Note that the CMP treatment may be performed only once or plural times.When the CMP treatment is performed plural times, it is preferable thatfirst polishing be performed at a high polishing rate and finalpolishing be performed at a low polishing rate. By performing polishingsteps with different polishing rates in combination, the planarity ofthe polished surface can be further increased.

Next, a conductor to be the conductor 420 is formed. Note that theconductor 420 may have a stacked-layer structure. The conductor to bethe conductor 420 can be formed by a sputtering method, a CVD method, anMBE method, a PLD method, an ALD method, or the like.

Next, the conductor to be the conductor 420 is processed by aphotolithography method or the like, so that the conductor 420 isformed.

Next, as illustrated in FIGS. 9C and 9D, the insulator 408 is formedover the insulator 410 and the conductor 420. The insulator 408 can beformed by a sputtering method, a CVD method, an MBE method, a PLDmethod, an ALD method, or the like. Aluminum oxide is preferably formedas the insulator 408 using plasma containing oxygen, so that oxygen inthe plasma can be added to the top surface of the insulator 410 asexcess oxygen (exO). Excess oxygen can be added to the insulator 408 bysupplying oxygen through the insulator 410. Here, the mixed regioncontaining a large amount of excess oxygen might be formed in theinterface between the insulator 408 and the insulator 410 and thevicinity of the interface.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Furthermore, second heat treatment may be performed at any time afterthe formation of the insulator 408. By the second heat treatment, theexcess oxygen contained in the insulator 410 and the mixed region 414 ismoved to the semiconductor 406 b through the insulator 412, theinsulator 402, the insulator 406 c, and the insulator 406 a. Sinceexcess oxygen is moved to the semiconductor 406 b as described above,defects (oxygen vacancies) in the semiconductor 406 b can be reduced.

Note that the second heat treatment may be performed at a temperaturesuch that excess oxygen in the insulator 410 and the mixed region 414 isdiffused to the semiconductor 406 b. For example, the description of thefirst heat treatment may be referred to for the second heat treatment.The second heat treatment is preferably performed at a temperature lowerthan that of the first heat treatment. The second heat treatment ispreferably performed at a temperature lower than that of the first heattreatment by higher than or equal to 20 □C and lower than or equal to150 □C, preferably higher than or equal to 40 □C and lower than or equalto 100 □C. Accordingly, superfluous release of excess oxygen from theinsulator 402 or the like can be inhibited. Note that the second heattreatment is not necessarily performed when heating during formation ofthe films can work as heat treatment comparable to the second heattreatment.

Although not illustrated, an opening reaching the conductor 416 a and anopening reaching the conductor 416 b may be formed in the insulator 408and the insulator 410, and conductors serving as wirings may be formedin the openings. Alternatively, an opening reaching the conductor 404may be formed in the insulator 408, and a conductor serving as a wiringmay be formed in the opening.

Through the above steps, the transistor illustrated in FIGS. 1A to 1Ccan be manufactured.

In Embodiment 1, one embodiment of the present invention has beendescribed. Note that one embodiment of the present invention is notlimited to the above examples. That is, since various embodiments of thepresent invention are disclosed in this embodiment and otherembodiments, one embodiment of the present invention is not limited to aspecific embodiment. The example in which an oxide semiconductor is usedas a semiconductor has been described as one embodiment of the presentinvention; however, one embodiment of the present invention is notlimited thereto. Depending on cases or conditions, silicon, germanium,silicon germanium, silicon carbide, gallium arsenide, aluminum galliumarsenide, indium phosphide, gallium nitride, an organic semiconductor,or the like may be used in one embodiment of the present invention.

The structure and method described in this embodiment can be implementedby being combined as appropriate with any of the other structures andmethods described in the other embodiments.

Embodiment 2 <Transistor Structure 2>

A transistor having a structure different from that in FIGS. 1A to 1Cand a manufacturing method thereof will be described with reference toFIGS. 2A to 2C. FIGS. 2A to 2C are a top view and cross-sectional viewsof a semiconductor device of one embodiment of the present invention.FIG. 2A is the top view, and FIGS. 2B and 2C are the cross-sectionalviews taken along dashed-dotted lines A1-A2 and A3-A4 in FIG. 2A,respectively. Note that for simplification of the drawing, somecomponents are not illustrated in the top view in FIG. 2A.

In the transistor in FIG. 2B, the angle θ between the side surface ofthe insulator 410 and a top surface of the conductor 416 a is greaterthan 0° and less than 90°, and the insulator 406 c is formed on the sidesurface of the insulator 410. The angle θ is preferably greater than orequal to 75 □C and less than 90 □C, preferably greater than or equal to80□□C and less than 90□□C, further preferably greater than or equal to85 □C and less than 90 □C. The insulator 406 c is formed thinner in aregion overlapping with a side surface of the conductor 404 with theinsulator 412 interposed therebetween than in a region overlapping withthe bottom surface of the conductor 404. For the other components, thedescription of the transistor in FIGS. 1A to 1C is referred to.

<Method 2 for Manufacturing Transistor>

First, the steps up to the step illustrated in FIG. 7H described inEmbodiment 1 are performed.

Next, the side surface of the insulator 410 is formed so that the angleθ between the side surface of the insulator 410 and the top surface ofthe conductor 416 a is greater than 0° and less than 90°□ Then, theinsulator 406 c is formed with use of the film formation apparatusdescribed in Embodiment 1. Here, for example, the smaller the angle θis, the higher the probability of deposition of sputtered particlesbecomes, in which case the insulator 406 c is formed thick on the sidesurface of the insulator 410. The insulator 406 c is formed thin on theside surface of the insulator 410 as the angle θ gets larger. In such amanner, the thickness of the insulator 406 c formed on the side surfaceof the insulator 410 can be adjusted by the angle θ□ That is, L1, whichis the width of the offset region to be formed, can be reduced.Accordingly, t1 is greater than L1, and L1/t1 is less than 1.

The subsequent steps may be performed in a manner similar to that of thesteps described in the method 1 for manufacturing the transistordescribed in Embodiment 1.

Through the above steps, the transistor illustrated in FIGS. 2A to 2Ccan be manufactured.

The structure and method described in this embodiment can be implementedby being combined as appropriate with any of the other structures andmethods described in the other embodiments.

Embodiment 3 <Transistor Structures 3 and 4>

Transistors having structures different from that in FIGS. 1A to 1C andmanufacturing methods thereof will be described with reference to FIGS.3A to 3C and FIGS. 4A to 4C. FIGS. 3A to 3C and FIGS. 4A to 4C are topviews and cross-sectional views of semiconductor devices of oneembodiment of the present invention.

The transistors illustrated in FIGS. 3A to 3C and FIGS. 4A to 4C aredescribed. FIG. 3A and FIG. 4A are top views. FIG. 3B is across-sectional view taken along dashed-dotted line A1-A2 in FIG. 3A.FIG. 3C is a cross-sectional view taken along dashed-dotted line A3-A4illustrated in FIG. 3A. Note that for simplification of the drawing,some components in the top view in FIG. 3A are not illustrated.

FIG. 4B is a cross-sectional view taken along dashed-dotted line A1-A2illustrated in FIG. 4A. FIG. 4C is a cross-sectional view taken alongdashed-dotted line A3-A4 illustrated in FIG. 4A. Note that forsimplification of the drawing, some components in the top view in FIG.4A are not illustrated.

In the transistors in FIGS. 3A to 3C and FIGS. 4A to 4C, the insulator406 c 2 (the insulator 406 c in FIGS. 4B and 4C), the insulator 412, theconductor 404 a, and the conductor 404 b are also formed in part of aregion on the top surface of the insulator 410. For the othercomponents, the description of the transistor in FIGS. 1A to 1C or thetransistor in FIGS. 2A to 2C is referred to.

In the transistors in FIGS. 3A to 3C and FIGS. 4A to 4C, part of theconductor 404 a and the conductor 404 b serving as a gate electrode mayfunction as a wiring. That is, part of the conductors 404 a and 404 bwhich is formed over the insulator 410 with the insulator 406 c and theinsulator 412 positioned therebetween correspond to the conductor 420 inthe transistor structure 1. That is, in the structure, t2 is theperpendicular distance between part of the conductor 404 a which is overthe insulator 410 and the conductor 416 a or the conductor 416 b. Notethat since the insulator 406 c 2, the insulator 412, the conductor 404a, and the conductor 404 b are formed at the same time, the insulator406 c 2 (an insulator 406 c in FIGS. 4B and 4C) and the insulator 412are positioned between the top surface of the insulator 410 and part ofthe conductor 404 a which is formed over the insulator 410. Therefore,t2, the length of the summation of the thicknesses of the insulator 410,the insulator 406 c 2 (the insulator 406 c in FIGS. 4B and 4C), and theinsulator 412, can be sufficiently large, so that parasitic capacitancecan be reduced.

<Methods 3 and 4 for Manufacturing Transistor>

A method for manufacturing the transistor illustrated in FIGS. 3A to 3Cis described below.

First, the steps up to the step illustrated in FIG. 8F described inEmbodiment 1 are performed.

Next, the insulator 406 c, the insulator 412, the conductor 404 a, andthe conductor 404 b are formed by a photolithography method or the like.With this structure, a conductor corresponding to the conductor 420 inthe transistor structure 1 can be formed at the same time using theconductor 404 a and the conductor 404 b.

Next, the insulator 408 is formed.

Through the above steps, the transistor illustrated in FIGS. 3A to 3Ccan be manufactured.

In the transistor in FIGS. 4A to 4C, the insulator 406 c, the insulator412, the conductor 404 a, and the conductor 404 b are formed in stepssimilar to those of the transistor illustrated in FIGS. 2A to 2C. Then,the insulator 406 c, the insulator 412, the conductor 404 a, and theconductor 404 b each having a desired shape are formed by aphotolithography method. With this structure, a conductor correspondingto the conductor 420 in the transistor structure 1 can be formed usingthe conductor 404 a and the conductor 404 b.

Through the above steps, the transistor illustrated in FIGS. 4A to 4Ccan be manufactured.

The structure and method described in this embodiment can be implementedby being combined as appropriate with any of the other structures andmethods described in the other embodiments.

Embodiment 4 <Transistor Structures 5 and 6>

Transistors having structures different from that in FIGS. 1A to 1C andmanufacturing methods thereof will be described with reference to FIGS.5A to 5C and FIGS. 6A to 6C. FIGS. 5A to 5C and FIGS. 6A to 6C are topviews and cross-sectional views of semiconductor devices of oneembodiment of the present invention.

The transistors illustrated in FIGS. 5A to 5C and FIGS. 6A to 6C aredescribed. FIG. 5A and FIG. 6A are top views. FIG. 5B is across-sectional view taken along dashed-dotted line A1-A2 in FIG. 5A.FIG. 5C is a cross-sectional view taken along dashed-dotted line A3-A4illustrated in FIG. 5A. Note that for simplification of the drawing,some components in the top view in FIG. 5A are not illustrated.

FIG. 6B is a cross-sectional view taken along dashed-dotted line A1-A2illustrated in FIG. 6A. FIG. 6C is a cross-sectional view taken alongdashed-dotted line A3-A4 illustrated in FIG. 6A. Note that forsimplification of the drawing, some components are not illustrated inthe top view in FIG. 6A.

In the transistors illustrated in FIGS. 5A to 5C and FIGS. 6A to 6C, theconductor 416 a and the conductor 416 b are formed only over thesemiconductor 406 b. For the other components, the description of thetransistor in FIGS. 1A to 1C or the transistor in FIGS. 2A to 2C isreferred to.

<Methods 5 and 6 for Manufacturing Transistor>

A method for manufacturing the transistor illustrated in FIGS. 5A to 5Cis described below.

First, the steps up to the step illustrated in FIGS. 7A and 7B describedin Embodiment 1 are performed.

Then, the conductor 416 is formed after the insulator 406 a and thesemiconductor 406 b are formed. Then, a resist is formed over theconductor 416 by a photolithography method or the like, and firstetching is performed on the conductor 416 using the resist as a mask.Then, after the resist is removed, a second etching is performed usingthe conductor 416 as a mask. The second etching is performed on theinsulator 406 a and the semiconductor 406 b.

The following steps are similar to the steps after the step illustratedin FIGS. 7G and 7H in Embodiment 1. Through the above steps, thetransistor illustrated in FIGS. 5A to 5C can be manufactured.

In the transistor illustrated in FIGS. 6A to 6C, the insulator 406 a,the semiconductor 406 b, and the conductor 416 are formed in a mannersimilar to that of the transistor illustrated in FIGS. 5A to 5C. Then,the transistor is preferably formed through the steps similar to thoseof the transistor illustrated in FIGS. 2A to 2C.

Through the above steps, the transistor illustrated in FIGS. 6A to 6Ccan be manufactured.

The structure and method described in this embodiment can be implementedby being combined as appropriate with any of the other structures andmethods described in the other embodiments.

Embodiment 5 <Transistor Structure 7>

A structure of a transistor included in a semiconductor device of oneembodiment of the present invention is described below.

FIGS. 10A to 10C are a top view and cross-sectional views of thesemiconductor device of one embodiment of the present invention. FIG.10A is the top view. FIG. 10B is a cross-sectional view taken alongdashed-dotted line A1-A2 in FIG. 10A, which illustrates across-sectional shape in the channel length direction. FIG. 10C is across-sectional view taken along dashed-dotted line A3-A4 in FIG. 10A,which illustrates a cross-sectional shape in the channel widthdirection. Note that for simplification of the drawing, some componentsin the top view in FIG. 10A are not illustrated.

A transistor illustrated in FIGS. 10A to 10C includes the conductor 413and the insulator 401 over a substrate 400, the insulator 402 over theconductor 413 and the insulator 401, the insulator 406 a over theinsulator 402, the semiconductor 406 b over the insulator 406 a, theconductor 416 a and the conductor 416 b each including a region incontact with a top surface of the semiconductor 406 b, the insulator 410that is in contact with top surfaces of the insulator 402, the conductor416 a and the conductor 416 b and has an opening, an insulator 406 c incontact with a side surface of the conductor 416 a and top and sidesurfaces of the semiconductor 406 b, an insulator 406 d over theinsulator 406 c, an insulator 412 in contact with a top surface of theinsulator 406 d and a side surface of the opening in the insulator 410,the conductor 404 including the conductor 404 a and the conductor 404 b,that is positioned over the semiconductor 406 b with the insulator 412,the insulator 406 c, and the insulator 406 d positioned therebetween.Note that the conductor 404 b faces the side surface of the opening inthe insulator 410 with the conductor 404 a and the insulator 412positioned therebetween. A conductor 420 over the conductors 404 a and404 b and an insulator 408 over the insulator 412 and the conductor 420are provided over a transistor. Alternatively, the conductor 413 and theinsulator 401 are not necessarily provided, and a structure without theconductor 413 and the insulator 401 as illustrated in FIGS. 56A to 56Cmay also be used.

Each of the insulator 406 c and the insulator 406 d preferably containsat least one element contained in the semiconductor 406 b other thanoxygen. This can reduce generation of defects at the interface betweenthe semiconductor 406 b and the insulator 406 c and the interfacebetween the insulator 406 c and the insulator 406 d. Furthermore, thecrystallinity of the insulator 406 c and the insulator 406 d can beimproved.

It is preferable that the semiconductor 406 b and the insulator 406 ceach include a CAAC-OS which will be described later. Furthermore, theinsulator 406 d preferably includes a CAAC-OS. Furthermore, theinsulator 406 a preferably includes a CAAC-OS.

In the transistor, the conductors 404 a and 404 b serve as a first gateelectrode. At least one of the conductors 404 a and 404 b is preferablya conductor that is less likely to transmit oxygen. For example, aconductor that is less likely to transmit oxygen is formed as theconductor 404 a that is a lower layer, in which case a reduction inconductivity caused by oxidization of the conductor 404 b can beprevented. The insulator 412 serves as a first gate insulator.

The conductor 413 serves as a second gate electrode. The conductor 413can have a stacked-layer structure including a conductor that is lesslikely to transmit oxygen. The stacked-layer structure including aconductor that is less likely to transmit oxygen can prevent a reductionin conductivity due to oxidation of the conductor 413. The insulator 402serves as a second gate insulator. The potential applied to theconductor 413 can control the threshold voltage of the transistor. Whenthe first gate electrode is electrically connected to the second gateelectrode, the current in a conducting state (on-state current) can beincreased. Note that the function of the first gate electrode and thatof the second gate electrode may be interchanged.

The conductor 416 a and the conductor 416 b serve as a source electrodeand a drain electrode. Note that conductivity of the conductor can bemeasured by a two-terminal method or the like.

Therefore, the resistance of the semiconductor 406 b can be controlledby a potential applied to the conductor 404. That is, conduction ornon-conduction between the conductors 416 a and 416 b can be controlledby the potential applied to the conductor 404.

As illustrated in FIG. 10B, the top surface of the semiconductor 406 bis in contact with the conductors 416 a 1 and 416 a 2. In addition, thesemiconductor 406 b can be electrically surrounded by an electric fieldof the conductor 404 serving as the gate electrode. A structure in whicha semiconductor is electrically surrounded by an electric field of agate electrode is referred to as a surrounded channel (s-channel)structure. Thus, in some cases, a channel is formed in the entiresemiconductor 406 b. In the s-channel structure, a large amount ofcurrent can flow between a source and a drain of the transistor, so thatan on-state current can be increased. In addition, since thesemiconductor 406 b is surrounded by the electric field of the conductor404, an off-state current can be decreased.

The transistor in this embodiment can also be referred to as atrench-gate self-aligned s-channel FET (TGSA s-channel FET) because theregion serving as a gate electrode is formed in a self-aligned manner tofill the opening formed in the insulator 410 and the like.

Here, in FIG. 10B, the length between a top surface of a region of thesemiconductor 406 b overlapping with the conductor 404 and a bottomsurface of the conductor 404 is denoted as t1. In FIG. 10B, the lengthbetween a region of the semiconductor 406 b overlapping with a bottomsurface of the conductor 416 a and a region of the semiconductor 406 boverlapping with the bottom surface of the conductor 404 is denoted asL1. Alternatively, the length between a region of the semiconductor 406b overlapping with a bottom surface of the conductor 416 b and theregion of the semiconductor 406 b overlapping with the bottom surface ofthe conductor 404 is denoted as L1.

In the transistor, a region having L1 is formed between a region where achannel is formed in the semiconductor 406 b (a region where theconductor 404 and the semiconductor 406 b overlap with each other) and asource region or a drain region (a region where the conductor 416 a orthe conductor 416 b overlaps with the semiconductor 406 b). The regionhaving L1 can reduce the off-state current of the transistor; however,the region with a too large L1 can reduce the on-state current of thetransistor.

The region where a channel is formed in the semiconductor 406 b iscovered with the insulator 406 c and the insulator 406 d, whereby theinsulator 406 c and the insulator 406 d can block entry of elementsother than oxygen (such as hydrogen and silicon) included in theadjacent insulator into the region where channel is formed. Therefore,the insulator 406 c and the insulator 406 d may be formed at least overthe semiconductor 406 b.

L1 can be reduced by not providing the insulator 406 c and the insulator406 d on a side surface of the conductor 404 with the insulator 412positioned therebetween or by forming the insulator 406 c and theinsulator 406 d thinner in a region covering the side surface of theconductor 404 with the insulator 412 positioned therebetween than in aregion overlapping with the bottom surface of the conductor 404 with theinsulator 412 positioned therebetween. Accordingly, t1 is greater thanL1, and L1/t1 is less than 1.

In FIGS. 10B and 11A, the length between the conductor 416 a or theconductor 416 b and the conductor 420 is denoted as t2. In addition, inFIG. 10B, the length between the conductor 416 a and the conductor 416 bis denoted as L2.

As the transistor is miniaturized, the parasitic capacitance in thevicinity of the transistor is a non-negligible and significant problem.For example, parasitic capacitance is in some cases formed between theconductor 420 and the conductor 416 a or the conductor 416 b. When thereis a large parasitic capacitance in the vicinity of the region where achannel is formed, for example, the transistor operation needs a timefor charging the parasitic capacitance, resulting in decreasing not onlythe responsiveness of the transistor but the responsiveness of thesemiconductor device. Furthermore, extra power consumption for chargingthe parasitic capacitance increases power consumption of a circuitincluding a plurality of transistors. Therefore, t2 is preferablysufficiently large such that the parasitic capacitance is negligiblysmall as compared to the gate capacitance.

L2 is reduced as the transistor is miniaturized, which leads todifficulty in applying a sufficiently large voltage to the conductor 404a and the conductor 404 b. However, when t2 has a sufficient length, theresistance of the conductor 404 a and that of the conductor 404 b can bereduced. Therefore, t2 is at least greater than L2, and t2/L2 ispreferably greater than or equal to 1.5 and less than or equal to 2.

FIGS. 11A and 11B are each an enlarged view of an opening provided inthe insulator 410 of the transistor in this embodiment. The top surfaceof the insulator 406 d is approximately the same level as the topsurfaces of the conductor 416 a and the conductor 416 b. Note that thetop surface of the insulator 406 d is a surface that is close to theconductor 404 a in a region where the insulator 406 d overlaps with thebottom surfaces of the conductor 404 a and the conductor 404 b. Ideally,the top surface of the insulator 406 d is preferably the same level asthe top surfaces of the conductors 416 a and 416 b as illustrated inFIG. 11A.

It is preferable that the top surface of the insulator 406 c beapproximately the same level as the interface between the semiconductor406 b and the conductors 416 a and 416 b. Note that the top surface ofthe insulator 406 c is a surface that is close to the conductor 404 a ina region where the insulator 406 c overlaps with the bottom surfaces ofthe conductor 404 a and the conductor 404 b. Ideally, the top surface ofthe insulator 406 c is preferably the same level as the interfacebetween the semiconductor 406 b and the conductors 416 a and 416 b. Notethat the insulator 406 c should at least fills in an over-etched portionof the semiconductor 406 b; however, it is not limited thereto, the topsurface of the insulator 406 c may be above the interface between thesemiconductor 406 b and the conductors 416 a and 416 b as illustrated inFIG. 11B.

The transistor of this embodiment has a structure in which twoinsulators, the insulators 406 c and 406 d, are provided over thesemiconductor 406 b; however, it is not limited thereto, three or morestacked layers may also be provided.

As the substrate 400, an insulator substrate, a semiconductor substrate,or a conductor substrate may be used, for example. As the insulatorsubstrate, a glass substrate, a quartz substrate, a sapphire substrate,a stabilized zirconia substrate (e.g., an yttria-stabilized zirconiasubstrate), or a resin substrate is used, for example. As thesemiconductor substrate, a single material semiconductor substrate ofsilicon, germanium, or the like or a compound semiconductor substrate ofsilicon carbide, silicon germanium, gallium arsenide, indium phosphide,zinc oxide, gallium oxide, or the like is used, for example. Asemiconductor substrate in which an insulator region is provided in theabove semiconductor substrate, e.g., a silicon on insulator (SOI)substrate or the like is used. As the conductor substrate, a graphitesubstrate, a metal substrate, an alloy substrate, a conductive resinsubstrate, or the like is used. A substrate including a metal nitride, asubstrate including a metal oxide, or the like is used. An insulatorsubstrate provided with a conductor or a semiconductor, a semiconductorsubstrate provided with a conductor or an insulator, a conductorsubstrate provided with a semiconductor or an insulator, or the like isused. Alternatively, any of these substrates over which an element isprovided may be used. As the element provided over the substrate, acapacitor, a resistor, a switching element, a light-emitting element, amemory element, or the like is used.

Alternatively, a flexible substrate may be used as the substrate 400. Asa method for providing a transistor over a flexible substrate, there isa method in which the transistor is formed over a non-flexible substrateand then the transistor is separated and transferred to the substrate400 which is a flexible substrate. In that case, a separation layer ispreferably provided between the non-flexible substrate and thetransistor. As the substrate 400, a sheet, a film, or a foil containinga fiber may be used. The substrate 400 may have elasticity. Thesubstrate 400 may have a property of returning to its original shapewhen bending or pulling is stopped. Alternatively, the substrate 400 mayhave a property of not returning to its original shape. The substrate400 has a region with a thickness of, for example, greater than or equalto 5 μm and less than or equal to 700 μm, preferably greater than orequal to 10 μm and less than or equal to 500 μm, more preferably greaterthan or equal to 15 μm and less than or equal to 300 μm. When thesubstrate 400 has a small thickness, the weight of the semiconductordevice including the transistor can be reduced. When the substrate 400has a small thickness, even in the case of using glass or the like, thesubstrate 400 may have elasticity or a property of returning to itsoriginal shape when bending or pulling is stopped. Therefore, an impactapplied to the semiconductor device over the substrate 400, which iscaused by dropping or the like, can be reduced. That is, a durablesemiconductor device can be provided.

For the substrate 400 which is a flexible substrate, metal, an alloy,resin, glass, or fiber thereof can be used, for example. The flexiblesubstrate 400 preferably has a lower coefficient of linear expansionbecause deformation due to an environment is suppressed. The flexiblesubstrate 400 is formed using, for example, a material whose coefficientof linear expansion is lower than or equal to 1×10⁻³/K, lower than orequal to 5×10⁻⁵/K, or lower than or equal to 1×10⁻⁵/K.

Examples of the resin include polyester, polyolefin, polyamide (e.g.,nylon or aramid), polyimide, polycarbonate, and acrylic. In particular,aramid is preferably used for the flexible substrate 400 because of itslow coefficient of linear expansion.

Note that electrical characteristics of the transistor can be stabilizedwhen the transistor is surrounded by an insulator with a function ofblocking oxygen and impurities such as hydrogen. For example, aninsulator with a function of blocking oxygen and impurities such ashydrogen may be used as the insulator 408.

An insulator with a function of blocking oxygen and impurities such ashydrogen may have a single-layer structure or a stacked-layer structureincluding an insulator containing, for example, boron, carbon, nitrogen,oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine,argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium,hafnium, or tantalum may be used.

For example, the insulator 408 may be formed of aluminum oxide,magnesium oxide, silicon nitride oxide, silicon nitride, gallium oxide,germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, or tantalum oxide. Note that theinsulator 408 preferably contains aluminum oxide. For example, when theinsulator 408 is formed using plasma containing oxygen, oxygen can beadded to the insulator 410 to be a base layer of the insulator 408 or aside surface of the insulator 412. The added oxygen becomes excessoxygen in the insulator 410 or the insulator 412. When the insulator 408contains aluminum oxide, entry of impurities such as hydrogen into thesemiconductor 406 b can be inhibited. In addition, when the insulator408 contains aluminum oxide, outward diffusion of excess oxygen that isadded to the insulator 410 and the insulator 412 can be reduced, forexample.

The insulator 402 may be formed to have, for example, a single-layerstructure or a stacked-layer structure including an insulator containingboron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum. For example, the insulator402 preferably contains silicon oxide or silicon oxynitride.

Note that the insulator 410 preferably includes an insulator with lowrelative dielectric constant. For example, the insulator 410 preferablycontains silicon oxide, silicon oxynitride, silicon nitride oxide,silicon nitride, silicon oxide to which fluorine is added, silicon oxideto which carbon is added, silicon oxide to which carbon and nitrogen areadded, silicon oxide having pores, a resin, or the like. Alternatively,the insulator 410 preferably has a stacked-layer structure of a resinand one of the following materials: silicon oxide, silicon oxynitride,silicon nitride oxide, silicon nitride, silicon oxide to which fluorineis added, silicon oxide to which carbon is added, silicon oxide to whichcarbon and nitrogen are added, and silicon oxide having pores. Whensilicon oxide or silicon oxynitride, which is thermally stable, iscombined with a resin, the stacked-layer structure can have thermalstability and low relative dielectric constant. Examples of the resininclude polyester, polyolefin, polyamide (e.g., nylon or aramid),polyimide, polycarbonate, and acrylic.

The insulator 412 may be formed to have, for example, a single-layerstructure or a stacked-layer structure including an insulator containingboron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum. For example, for theinsulator 412, a material containing silicon oxide or silicon oxynitrideis preferably used.

Note that the insulator 412 preferably contains an insulator with a highdielectric constant. For example, the insulator 412 preferably includesgallium oxide, hafnium oxide, oxide including aluminum and hafnium,oxynitride including aluminum and hafnium, oxide including silicon andhafnium, oxynitride including silicon and hafnium, or the like. Theinsulator 412 preferably has a stacked-layer structure including siliconoxide or silicon oxynitride and an insulator with a high dielectricconstant. Because silicon oxide and silicon oxynitride have thermalstability, combination of silicon oxide or silicon oxynitride with aninsulator with a high dielectric constant allows the stacked-layerstructure to be thermally stable and have a high dielectric constant.For example, when an aluminum oxide, a gallium oxide, or a hafnium oxideof the insulator 412 is on the insulators 406 c and 406 d side, entry ofsilicon included in the silicon oxide or the silicon oxynitride into thesemiconductor 406 b can be suppressed. When silicon oxide or siliconoxynitride is on the insulators 406 c and 406 d side, for example, trapcenters might be formed at the interface between aluminum oxide, galliumoxide, or hafnium oxide and silicon oxide or silicon oxynitride. Thetrap centers can shift the threshold voltage of the transistor in thepositive direction by trapping electrons in some cases.

Each of the conductors 416 a and 416 a may be formed to have asingle-layer structure or a stacked-layer structure including aconductor containing, for example, one or more kinds of boron, nitrogen,oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium,manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium,molybdenum, ruthenium, platinum, silver, indium, tin, tantalum, andtungsten. For example, an alloy film or a compound film may be used: aconductor containing aluminum, a conductor containing copper andtitanium, a conductor containing copper and manganese, a conductorcontaining indium, tin, and oxygen, a conductor containing titanium andnitrogen, or the like may be used.

Each of the conductors 404, 413, and 420 may be formed to have asingle-layer structure or a stacked-layer structure including aconductor containing, for example, one or more kinds of boron, nitrogen,oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium,manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium,molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. Forexample, an alloy film or a compound film may be used: a conductorcontaining aluminum, a conductor containing copper and titanium, aconductor containing copper and manganese, a conductor containingindium, tin, and oxygen, a conductor containing titanium and nitrogen,or the like may be used.

An oxide semiconductor is preferably used as the semiconductor 406 b.However, silicon (including strained silicon), germanium, silicongermanium, silicon carbide, gallium arsenide, aluminum gallium arsenide,indium phosphide, gallium nitride, an organic semiconductor, or the likecan be used in some cases.

As the insulator 406 a, the insulator 406 c, and the insulator 406 d,oxides containing one or more elements other than oxygen contained inthe semiconductor 406 b are preferably used. However, silicon (includingstrained silicon), germanium, silicon germanium, silicon carbide,gallium arsenide, aluminum gallium arsenide, indium phosphide, galliumnitride, an organic semiconductor, or the like can be used in somecases.

The semiconductor 406 b is an oxide semiconductor containing indium, forexample. The semiconductor 406 b can have high carrier mobility(electron mobility) by containing indium, for example. The semiconductor406 b preferably contains an element M. The element M is preferablyaluminum, gallium, yttrium, tin, or the like. Other elements which canbe used as the element M are boron, silicon, titanium, iron, nickel,germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium,tantalum, tungsten, magnesium, and the like. Note that two or more ofthe above elements may be used in combination as the element M. Theelement M is an element having high bonding energy with oxygen, forexample. The element M is an element whose bonding energy with oxygen ishigher than that of indium. The element M is an element that canincrease the energy gap of the oxide semiconductor, for example.Furthermore, the semiconductor 406 b preferably contains zinc. When theoxide semiconductor contains zinc, the oxide semiconductor is easily tobe crystallized, for example.

Note that the semiconductor 406 b is not limited to the oxidesemiconductor containing indium. The semiconductor 406 b may be, forexample, an oxide semiconductor which does not contain indium andcontains zinc, an oxide semiconductor which does not contain indium andcontains gallium, or an oxide semiconductor which does not containindium and contains tin, e.g., a zinc tin oxide or a gallium tin oxide.

For the semiconductor 406 b, an oxide with a wide energy gap may beused. For example, the energy gap of the semiconductor 406 b is greaterthan or equal to 2.5 eV and less than or equal to 4.2 eV, preferablygreater than or equal to 2.8 eV and less than or equal to 3.8 eV, morepreferably greater than or equal to 3 eV and less than or equal to 3.5eV.

The insulator 406 a, the insulator 406 c, and the insulator 406 d areoxides including one or more elements, or two or more elements otherthan oxygen included in the semiconductor 406 b. Since the insulator 406a, the insulator 406 c, and the insulator 406 d each include one or moreelements, or two or more elements other than oxygen included in thesemiconductor 406 b, a defect state is less likely to be formed at theinterface between the insulator 406 a and the semiconductor 406 b, theinterface between the semiconductor 406 b and the insulator 406 c, andthe interface between the insulator 406 c and the insulator 406 d.

As the semiconductor 406 b, an oxide having an electron affinity higherthan those of the insulators 406 a, 406 c, and 406 d is used. Forexample, as the semiconductor 406 b, an oxide having an electronaffinity higher than those of the insulators 406 a, 406 c, and 406 d by0.07 eV or higher and 1.3 eV or lower, preferably 0.1 eV or higher and0.7 eV or lower, or further preferably 0.15 eV or higher and 0.4 eV orlower is used. Note that the electron affinity refers to an energy gapbetween the vacuum level and the bottom of the conduction band.Furthermore, the insulator 406 c preferably has a higher electronaffinity than the insulator 406 d.

When gate voltage is applied to such a transistor in which the insulator406 a is placed under the semiconductor 406 b and the insulators 406 cand 406 d are placed over the semiconductor 406 b, a channel is formedin the semiconductor 406 b whose electron affinity is the highest amongthe insulator 406 a, the semiconductor 406 b, the insulator 406 c, andthe insulator 406 d. In this manner, a buried channel structure can beformed.

Here, in some cases, there is a mixed region of the insulator 406 a andthe semiconductor 406 b between the insulator 406 a and thesemiconductor 406 b. Furthermore, in some cases, there is a mixed regionof the semiconductor 406 b and the insulator 406 c between thesemiconductor 406 b and the insulator 406 c. Furthermore, in some cases,there is a mixed region of the insulator 406 c and the insulator 406 dbetween the insulator 406 c and the insulator 406 d. The mixed regionhas a low density of defect states. For that reason, in a stackincluding the insulator 406 a, the semiconductor 406 b, the insulator406 c, and the insulator 406 d energy changes continuously at theirinterfaces and in the vicinity of the interface (continuous junction).Note that boundaries of the insulator 406 a, the semiconductor 406 b,and the insulator 406 c are not clear in some cases.

At this time, electrons move mainly in the semiconductor 406 b, not inthe insulator 406 a, the insulator 406 c, and the insulator 406 d.

As factors of inhibiting electron movement are decreased, the on-statecurrent of the transistor can be increased. Electron movement isinhibited, for example, in the case where physical unevenness in achannel formation region is large.

To increase the on-state current of the transistor, for example, rootmean square (RMS) roughness with a measurement area of 1 μm×1 μm of thetop surface or the bottom surface of the semiconductor 406 b (aformation surface; here, the top surface of the insulator 406 a) is lessthan 1 nm, preferably less than 0.6 nm, further preferably less than 0.5nm, still further preferably less than 0.4 nm. The average surfaceroughness (also referred to as Ra) with the measurement area of 1 μm×1μm is less than 1 nm, preferably less than 0.6 nm, further preferablyless than 0.5 nm, still further preferably less than 0.4 nm. The maximumdifference (P−V) with the measurement area of 1 μm×1 μm is less than 10nm, preferably less than 9 nm, further preferably less than 8 nm, stillfurther preferably less than 7 nm. RMS roughness, Ra, and P−V can bemeasured using a scanning probe microscope SPA-500 manufactured by SIINano Technology Inc.

The above four-layer structure is an example. For example, astacked-layer structure in which any one of the insulators described asexamples of the insulator 406 a, the insulator 406 c, and the insulator406 d is provided below or over the insulator 406 a or below or over theinsulator 406 d may be employed.

Note that an oxide semiconductor which can be used for the semiconductorwill be described in detail in another embodiment.

<Method 7 for Manufacturing Transistor>

A method for manufacturing the transistor of the present invention inFIGS. 10A to 10C will be described below with reference to FIGS. 18A to18H, FIGS. 19A to 19F, and FIGS. 20A to 20F.

First, the substrate 400 is prepared.

Next, as illustrated in FIGS. 18A and 18B, the insulator to be theinsulator 401 is formed over the substrate 400. An opening is formed inthe insulator 401, and the conductor to be the conductor 413 is formedover the insulator 401. The conductor to be the conductor 413 can beformed by a sputtering method, a CVD method, an MBE method, a PLDmethod, an ALD method, or the like. The conductor 413 may have amultilayer structure including a conductor that is less likely totransmit oxygen. The conductor 413 may be embedded to the opening in theinsulator 401 by chemical mechanical polishing (CMP) or the like.Alternatively, the conductor 413 may be formed in such a manner that aconductor is formed and processed by a photolithography method or thelike.

In the photolithography method, first, a resist is exposed to lightthrough a photomask. Next, a region exposed to light is removed or leftusing a developing solution, so that a resist mask is formed. Then,etching through the resist mask is conducted. As a result, theconductor, the semiconductor, the insulator, or the like can beprocessed into a desired shape. The resist mask is formed by, forexample, exposure of the resist to light using KrF excimer laser light,ArF excimer laser light, extreme ultraviolet (EUV) light, or the like.Alternatively, a liquid immersion technique may be employed in which aportion between a substrate and a projection lens is filled with liquid(e.g., water) to perform light exposure. An electron beam or an ion beammay be used instead of the above-mentioned light. Note that dry etchingtreatment such as ashing or wet etching treatment can be used forremoval of the resist mask. Alternatively, wet etching treatment isperformed after dry etching treatment. Further alternatively, dryetching treatment is performed after wet etching treatment.

As a dry etching apparatus, a capacitively coupled plasma (CCP) etchingapparatus including parallel plate type electrodes can be used. Thecapacitively coupled plasma etching apparatus including the parallelplate type electrodes may have a structure in which a high-frequencypower source is applied to one of the parallel plate type electrodes.Alternatively, the capacitively coupled plasma etching apparatus mayhave a structure in which different high-frequency power sources areapplied to one of the parallel plate type electrodes. Alternatively, thecapacitively coupled plasma etching apparatus may have a structure inwhich high-frequency power sources with the same frequency are appliedto the parallel plate type electrodes. Alternatively, the capacitivelycoupled plasma etching apparatus may have a structure in whichhigh-frequency power sources with different frequencies are applied tothe parallel plate type electrodes. Alternatively, a dry etchingapparatus including a high-density plasma source can be used. As the dryetching apparatus including a high-density plasma source, an inductivelycoupled plasma (ICP) etching apparatus can be used, for example.

Next, as indicated by arrows in FIGS. 18A and 18B, high-density-plasmatreatment may be performed. High-density-plasma treatment is preferablyperformed in an oxygen atmosphere or a nitrogen atmosphere. The oxygenatmosphere is a gas atmosphere containing oxygen atoms, which includesatmospheres of oxygen, ozone, and nitrogen oxide (e.g., nitrogenmonoxide, nitrogen dioxide, dinitrogen monoxide, dinitrogen trioxide,dinitrogen tetroxide, or dinitrogen pentoxide). In the oxygenatmosphere, an inert gas such as nitrogen or a rare gas (e.g., helium orargon) may be included. When high-density plasma treatment is performedin an oxygen atmosphere in such a manner, carbon, hydrogen, or the likecan be released. In addition, in the case where high-density-plasmatreatment is performed in an oxygen atmosphere, organic compound such ashydrocarbon can be easily released from an object.

The high-density plasma treatment in a nitrogen atmosphere may behigh-density plasma treatment in an atmosphere containing nitrogen and arare gas, an atmosphere containing nitrogen, hydrogen, and a rare gas,or an atmosphere containing ammonia and a rare gas, for example. Withthis high-density plasma treatment in a nitrogen atmosphere, a surfaceof the treated object and its vicinity can be nitrided. The nitridedregion can be formed to be extremely thin on the surface side of thetreated object. This nitrided region can prevent diffusion ofimpurities.

After the high-density plasma treatment in an oxygen atmosphere isperformed, the high-density plasma treatment in a nitrogen atmospheremay be performed. Alternatively, after the high-density plasma treatmentin a nitrogen atmosphere is performed, the high-density plasma treatmentin an oxygen atmosphere may be performed. Annealing treatment may beperformed before or after each high-density plasma treatment. Note thatit is in some cases preferable to let an enough amount of gas flow inorder to increase the plasma density. When the gas amount is not enough,the deactivation rate of radicals becomes higher than the generationrate of radicals in some cases. For example, it is preferable in somecases to let a gas flow at 100 sccm or more, 300 sccm or more, or 800sccm or more.

The high-density plasma treatment is performed using a microwavegenerated with a high-frequency generator that generates a wave having afrequency of, for example, more than or equal to 0.3 GHz and less thanor equal to 3.0 GHz, more than or equal to 0.7 GHz and less than orequal to 1.1 GHz, or more than or equal to 2.2 GHz and less than orequal to 2.8 GHz (typically, 2.45 GHz). The treatment pressure can behigher than or equal to 10 Pa and lower than or equal to 5000 Pa,preferably higher than or equal to 200 Pa and lower than or equal to1500 Pa, further preferably higher than or equal to 300 Pa and lowerthan or equal to 1000 Pa. The substrate temperature can be higher thanor equal to 100° C. and lower than or equal to 600° C. (typically 400°C.). Furthermore, a mixed gas of oxygen and argon can be used.

For example, the high density plasma is generated using a 2.45 GHzmicrowave and preferably has an electron density of higher than or equalto 1×10¹¹/cm³ and lower than or equal to 1×10¹³/cm³, an electrontemperature of 2 eV or lower, or an ion energy of 5 eV or lower. Suchhigh-density plasma treatment produces radicals with low kinetic energyand causes little plasma damage, compared with conventional plasmatreatment. Thus, formation of a film with few defects is possible. Thedistance between an antenna that generates the microwave and the treatedobject is longer than or equal to 5 mm and shorter than or equal to 120mm, preferably longer than or equal to 20 mm and shorter than or equalto 60 mm.

Alternatively, a plasma power source that applies a radio frequency (RF)bias to a substrate may be provided. The frequency of the RF bias may be13.56 MHz, 27.12 MHz, or the like, for example. The use of high-densityplasma enables high-density oxygen ions to be produced, and applicationof the RF bias to the substrate allows oxygen ions generated by thehigh-density plasma to be efficiently introduced into the treatedobject. Therefore, it is preferable to perform the high-density plasmatreatment while a bias is applied to the substrate.

Following the high-density plasma treatment, annealing treatment may besuccessively performed without an exposure to the air. Followingannealing treatment, the high-density plasma treatment may besuccessively performed without an exposure to the air. By performinghigh-density plasma treatment and annealing treatment in succession,entry of impurities during the treatment can be suppressed. Moreover, byperforming annealing treatment after the high-density plasma treatmentin an oxygen atmosphere, unnecessary oxygen that is added into thetreated object but is not used to fill oxygen vacancies can beeliminated. The annealing treatment may be performed by lamp annealingor the like, for example.

The treatment time of the high-density plasma treatment is preferablylonger than or equal to 30 seconds and shorter than or equal to 120minutes, longer than or equal to 1 minute and shorter than or equal to90 minutes, longer than or equal to 2 minutes and shorter than or equalto 30 minutes, or longer than or equal to 3 minutes and shorter than orequal to 15 minutes.

The treatment time of the annealing treatment at a temperature of higherthan or equal to 250° C. and lower than or equal to 800° C., higher thanor equal to 300° C. and lower than or equal to 700° C., or higher thanor equal to 400° C. and lower than or equal to 600° C. is preferablylonger than or equal to 30 seconds and shorter than or equal to 120minutes, longer than or equal to 1 minute and shorter than or equal to90 minutes, longer than or equal to 2 minutes and shorter than or equalto 30 minutes, or longer than or equal to 3 minutes and shorter than orequal to 15 minutes.

Next, the insulator 402 is formed. The insulator 402 may be formed by asputtering method, a chemical vapor deposition (CVD) method, a molecularbeam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, anatomic layer deposition (ALD) method, or the like.

CVD methods can be classified into a plasma enhanced CVD (PECVD) methodusing plasma, a thermal CVD (TCVD) method using heat, a photo CVD methodusing light, and the like. Moreover, the CVD method can include a metalCVD (MCVD) method and a metal organic CVD (MOCVD) method depending on asource gas.

By using the PECVD method, a high-quality film can be formed at arelatively low temperature. Furthermore, a thermal CVD method does notuse plasma and thus causes less plasma damage to an object. For example,a wiring, an electrode, an element (e.g., transistor or capacitor), orthe like included in a semiconductor device might be charged up byreceiving charges from plasma. In that case, accumulated charges mightbreak the wiring, electrode, element, or the like included in thesemiconductor device. By contrast, when a thermal CVD method not usingplasma is employed, such damage due to exposure to plasma is not causedand the yield of the semiconductor device can be increased. In a thermalCVD method, an object is not exposed to plasma during deposition, sothat a film with few defects can be obtained.

An ALD method also causes less plasma damage to an object. An ALD methoddoes not cause plasma damage during deposition, so that a film with fewdefects can be obtained.

Unlike in a deposition method in which particles ejected from a targetor the like are deposited, in a CVD method and an ALD method, a film isformed by reaction at a surface of an object. Thus, a CVD method and anALD method enable favorable step coverage almost regardless of the shapeof an object. In particular, an ALD method enables excellent stepcoverage and excellent thickness uniformity and can be favorably usedfor covering a surface of an opening with a high aspect ratio, forexample. On the other hand, an ALD method has a low deposition rate;thus, it is sometimes preferable to combine an ALD method with anotherdeposition method with a high deposition rate such as a CVD method.

When a CVD method or an ALD method is used, composition of a film to beformed can be controlled with a flow rate ratio of the source gases. Forexample, by a CVD method or an ALD method, a film with a certaincomposition can be formed depending on a flow rate ratio of the sourcegases. Moreover, with a CVD method or an ALD method, by changing theflow rate ratio of the source gases while forming the film, a film whosecomposition is continuously changed can be formed. In the case where thefilm is formed while changing the flow rate ratio of the source gases,as compared to the case where the film is formed using a plurality ofdeposition chambers, time taken for the film formation can be reducedbecause time taken for transfer and pressure adjustment is omitted.Thus, semiconductor devices can be manufactured with improvedproductivity.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

In addition, treatment to add oxygen to the insulator 402 may beperformed. For the treatment to add oxygen, an ion implantation method,a plasma treatment method, or the like can be used. Note that oxygenadded to the insulator 402 is excess oxygen.

Next, as illustrated in FIGS. 18C and 18D, the insulator to be theinsulator 406 a, the semiconductor to be the semiconductor 406 b, andthe resist mask 430 are formed.

First, the insulator to be the insulator 406 a is formed over theinsulator 402. The insulator to be the insulator 406 a can be formed bya sputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like. It is particularly preferable to use afacing-target sputtering apparatus. Note that in this specification andthe like, deposition using a facing-target sputtering apparatus can alsobe referred to as vapor deposition sputtering (VDSP).

The use of the facing-target sputtering apparatus can reduce plasmadamage induced during deposition of the insulator. Thus, oxygenvacancies in the insulator can be reduced. In addition, the use of thefacing-target sputtering apparatus allows deposition in high vacuum. Inthat case, impurity concentration (e.g., concentration of hydrogen, arare gas (such as argon), or water) in the deposited insulator can bereduced.

Alternatively, a sputtering apparatus including an inductively-coupledantenna conductor plate may be used. Thus, a large film with highuniformity can be formed with a high deposition rate.

Deposition is preferably performed using a gas containing oxygen, a raregas, a gas containing nitrogen, or the like. As the gas containingnitrogen, nitrogen (N₂), dinitrogen oxide (N₂O), ammonia (NH₃), or thelike may be used, for example.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case wherehigh-density-plasma treatment is performed under an oxygen atmosphere,organic compounds such as hydrocarbons can be released from an object.

In addition, treatment to add oxygen to the insulator to be theinsulator 406 a may be performed. For the treatment to add oxygen, anion implantation method, a plasma treatment method, or the like can beused. Note that oxygen added to the insulator to be the insulator 406 ais excess oxygen.

Next, the semiconductor to be the semiconductor 406 b is formed over theinsulator to be the insulator 406 a. The semiconductor can be formed bya sputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like. It is particularly preferable to use afacing-target sputtering apparatus.

The use of the facing-target sputtering apparatus can reduce plasmadamage induced during deposition of the semiconductor. Accordingly,oxygen vacancies in the semiconductor can be reduced. In addition, theuse of the facing-target sputtering apparatus allows deposition in highvacuum. In that case, impurity concentration (e.g., concentration ofhydrogen, a rare gas (such as argon), or water) in the depositedsemiconductor can be reduced.

Alternatively, a sputtering apparatus including an inductively-coupledantenna conductor plate may be used. Thus, a large film with highuniformity can be formed with a high deposition rate.

Deposition is preferably performed using a gas containing oxygen, a raregas, a gas containing nitrogen, or the like. As the gas containingnitrogen, nitrogen (N₂), dinitrogen oxide (N₂O), or ammonia (NH₃) may beused, for example.

Next, first heat treatment is preferably performed. The first heattreatment can be performed at a temperature higher than or equal to 250°C. and lower than or equal to 650° C., preferably higher than or equalto 450° C. and lower than or equal to 600° C. The first heat treatmentis performed in an inert gas atmosphere or an atmosphere containing anoxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The firstheat treatment may be performed under a reduced pressure. Alternatively,the first heat treatment may be performed in such a manner that heattreatment is performed in an inert gas atmosphere, and then another heattreatment is performed in an atmosphere containing an oxidizing gas at10 ppm or more, 1% or more, or 10% or more in order to compensatedesorbed oxygen. By the first heat treatment, crystallinity of thesemiconductor can be increased and impurities such as hydrogen andmoisture can be removed, for example. Alternatively, in the first heattreatment, plasma treatment using oxygen may be performed under areduced pressure. The plasma treatment containing oxygen is preferablyperformed using an apparatus including a power source for generatinghigh-density plasma using microwaves, for example. Alternatively, aplasma power source for applying a radio frequency (RF) voltage to asubstrate side may be provided. The use of high-density plasma enableshigh-density oxygen radicals to be produced, and application of the RFvoltage to the substrate side allows oxygen radicals generated by thehigh-density plasma to be efficiently introduced into the semiconductor406 b. Alternatively, after plasma treatment using an inert gas with theapparatus, plasma treatment using oxygen in order to compensate releasedoxygen may be performed.

Next, the insulator to be the insulator 406 a and the semiconductor tobe the semiconductor 406 b are processed by a photolithography method orthe like using a resist mask 430 to form a multilayer film including theinsulator 406 a and the semiconductor 406 b as illustrated in FIGS. 18Eand 18F. Note that when the multilayer film is formed, the insulator 402is also subjected etching to have a thinned region in some cases. Thatis, the insulator 402 may have a protruding portion in a region incontact with the multilayer film.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, as illustrated in FIGS. 18G and 18H, the conductor 416 and theinsulator to be the insulator 410 are formed.

First, the conductor 416 is formed. The conductor 416 can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like.

Note that the conductor 416 covers the multilayer film. The side surfaceof the insulator 406 a and the top and side surfaces of thesemiconductor 406 b are partly damaged in forming the conductor over themultilayer film, and then a region where resistance is reduced might beformed. Since each of the insulator 406 a and the semiconductor 406 bincludes a region whose resistance is lowered, the contact resistancebetween the conductor 416 and the semiconductor 406 b can be lowered.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, the conductor 416 is processed by a photolithography method or thelike, so that the conductors 416 a and 416 b are formed.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, the insulator to be the insulator 410 is formed. The insulator tobe the insulator 410 can be formed by a sputtering method, a CVD method,an MBE method, a PLD method, an ALD method, or the like. Alternatively,the insulator to be the insulator 410 can be formed by a spin coatingmethod, a dipping method, a droplet discharging method (such as anink-jet method), a printing method (such as screen printing or offsetprinting), a doctor knife method, a roll coater method, a curtain coatermethod, or the like.

The insulator to be the insulator 410 may be formed to have a flat topsurface. For example, the top surface of the insulator to be theinsulator 410 may have planarity immediately after the film formation.Alternatively, after the film formation, an upper portion of theinsulator to be the insulator 410 may be removed so that the top surfaceof the insulator to be the insulator 410 becomes parallel to a referencesurface such as a rear surface of the substrate. Such treatment isreferred to as planarization treatment. As the planarization treatment,for example, chemical mechanical polishing treatment, dry etchingtreatment, or the like can be performed. However, the top surface of theinsulator to be the insulator 410 is not necessarily flat.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, a resist mask 431 is formed over the insulator to be the insulator410 by a photolithography method or the like. Here, an organic coatingfilm may be formed between the top surface of the insulator to be theinsulator 410 and the resist mask 431 in order to improve the adhesionbetween the top surface of the insulator to be the insulator 410 and theresist mask 431.

Next, as illustrated in FIGS. 19A and 19B, an opening is formed in theinsulator 410 and the conductor 416. First, the insulator to be theinsulator 410 is subjected to a first processing by a dry etching methodor the like to expose the top surface of the conductor 416. In a dryetching method, any of the above dry etching apparatuses can be used;however, a dry etching apparatus in which high-frequency power sourceswith different frequencies are connected to the parallel-plateelectrodes is preferably used.

Next, the conductor 416 is subjected to a second processing by a dryetching method or the like so as to be separated into the conductor 416a and the conductor 416 b. Note that the insulator 410 and the conductor416 may be processed in the same photolithography process. Processing inthe same photolithography process can reduce the number of manufacturingsteps. Thus, a semiconductor device including the transistor can bemanufactured with high productivity.

At this time, the semiconductor 406 b has a region that is exposed. Theexposed region of the semiconductor 406 b is partly removed by thesecond processing in some cases. Furthermore, impurity elements such asresidual components of the etching gas are attached to the exposedsurface of the semiconductor 406 b in some cases. For example, chlorineand the like may be attached when a chlorine-based gas is used as theetching gas. When a hydrocarbon-based gas is used as the etching gas,carbon, hydrogen, and the like may be attached. The impurity elementsattached to the exposed surface of the semiconductor 406 b arepreferably reduced. The impurity elements can be reduced by cleaningtreatment using dilute hydrofluoric acid, cleaning treatment usingozone, cleaning treatment using ultra violet rays, or the like. Notethat some kinds of cleaning treatment may be used in combination.Accordingly, the exposed surface of the semiconductor 406 b, that is,the region where channel is formed has a high resistance.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, as illustrated in FIGS. 19C and 19D, the insulator 406 c is formedover top and side surfaces of the semiconductor 406 b, a side surface ofthe insulator 406 a, a top surface of the insulator 402, and a topsurface of the insulator 410, which are surfaces except for at least theside surface of the insulator 410. Note that the insulator 406 c ispreferably formed so as to fill in a depression formed in thesemiconductor 406 b. The insulator 406 c can be formed by a sputteringmethod.

Here, a sputtering apparatus which is used for formation of theinsulator 406 c and the insulator 406 d is described with reference toFIG. 21 and FIG. 22.

FIG. 21 is a cross-sectional view illustrating part of a sputteringapparatus 101. The sputtering apparatus 101 illustrated in FIG. 21includes a member 190, a collimator 150 over the member 190, a targetholder 120, a backing plate 110 placed over the target holder 120, atarget 100 placed over the backing plate 110, a magnet unit 130including a magnet 130N and a magnet 130S placed under the target 100with the backing plate 110 positioned therebetween, and a magnet holder132 that supports the magnet unit 130. Note that in this specification,a magnet unit means a group of magnets. The magnet unit can be replacedwith “cathode”, “cathode magnet”, “magnetic member”, “magnetic part”, orthe like.

A substrate stage 170 placed to face the target 100 and a substrate 160held by the substrate stage 170 are illustrated. FIG. 21 alsoillustrates a magnetic force line 180 a and a magnetic force line 180 bformed by the magnet unit 130.

The target holder 120 and the backing plate 110 are fixed to each otherwith a bolt and have the same potential. The target holder 120 has afunction of supporting the target 100 with the backing plate 110positioned therebetween.

The backing plate 110 has a function of fixing the target 100.

The sputtering apparatus 101 may have a water channel inside or underthe backing plate 110. By making fluid (air, nitrogen, a rare gas,water, oil, or the like) flow through the water channel, dischargeanomaly due to an increase in the temperature of the target 100 ordamage to the sputtering apparatus 101 due to deformation of a componentsuch as the target 100 can be prevented in the sputtering. In that case,the backing plate 110 and the target 100 are preferably adhered to eachother with a bonding member because the cooling capability is increased.

A gasket is preferably provided between the target holder 120 and thebacking plate 110, in which case an impurity is less likely to enter thesputtering apparatus 101 from the outside or the water channel.

In the magnet unit 130, the magnet 130N and the magnet 130S are placedsuch that their surfaces on the target 100 side have oppositepolarities. Here, the case where the pole of the magnet 130N on thetarget 100 side is the north pole and the pole of the magnet 130S on thetarget 100 side is the south pole is described. Note that the layout ofthe magnets and the poles in the magnet unit 130 are not limited tothose illustrated in FIG. 21.

The magnetic force line 180 a is one of magnetic force lines that form ahorizontal magnetic field in the vicinity of the top surface of thetarget 100. The vicinity of the top surface of the target 100corresponds to a region in which the perpendicular distance from the topsurface of the target 100 is, for example, greater than or equal to 0 mmand less than or equal to 10 mm, in particular, greater than or equal to0 mm and less than or equal to 5 mm.

The magnetic force line 180 b is one of magnetic force lines that form ahorizontal magnetic field in a plane apart from the top surface of themagnet unit 130 by a perpendicular distance d. The perpendiculardistance d is, for example, greater than or equal to 0 mm and less thanor equal to 20 mm or greater than or equal to 5 mm and less than orequal to 15 mm.

In the deposition, a potential V1 applied to the target holder 120 is,for example, lower than a potential V2 applied to the substrate stage170. The potential V2 applied to the substrate stage 170 is, forexample, the ground potential. A potential V3 applied to the magnetholder 132 is, for example, the ground potential. Note that thepotentials V1, V2, and V3 are not limited to the above description. Notall the target holder 120, the substrate stage 170, and the magnetholder 132 are necessarily supplied with potentials. For example, thesubstrate stage 170 may be electrically floating.

FIG. 21 illustrates an example where the backing plate 110 and thetarget holder 120 are not electrically connected to the magnet unit 130and the magnet holder 132, but electrical connection is not limitedthereto. For example, the backing plate 110 and the target holder 120may be electrically connected to the magnet unit 130 and the magnetholder 132, and the backing plate 110, the target holder 120, the magnetunit 130, and the magnet holder 132 may have the same potential.

When the potential V1 is applied to the target holder 120 under theconditions that the deposition gas (e.g., oxygen, nitrogen, or a raregas such as argon) flows in the sputtering apparatus 101 and thepressure in the sputtering apparatus 101 is constant (e.g., greater thanor equal to 0.05 Pa and less than or equal to 10 Pa, preferably greaterthan or equal to 0.1 Pa and less than or equal to 0.8 Pa), a plasma isformed in a magnetic field formed by the magnet unit 130. The potentialof the plasma is a potential Vp that is higher than the potential V1. Atthis time, a cation in the plasma is accelerated toward the target 100by a potential difference between the potential Vp and the potential V1.Then, the cation collides with the target 100 to release sputteredparticles 194. The released sputtered particles that reach the substrate160 are deposited to form a film.

In a sputtering apparatus in general, a sputtered particle is lesslikely to reach a bottom portion of a small opening with a high aspectratio. In addition, a sputtered particle, which flies in the obliquedirection to the substrate, is deposited in the vicinity of upper partof an opening, which narrows the width of the upper part of the opening.In that case, the sputtered particle is not formed in the opening.

In contrast, with use of the sputtering apparatus with the abovestructure, released sputtered particles that fly in the obliquedirection to the formation surface of the substrate 160 are attached tothe collimator 150. That is, sputtered particles having a perpendicularcomponent to the substrate 160, which have passed through the collimator150 provided between the target 100 and the substrate 160, reach thesubstrate. Thus, sputtered particles are deposited on a plane parallelto the substrate. On the other hand, sputtered particles are notdeposited on a plane perpendicular to the substrate, or the amount ofdeposition thereof on the plane perpendicular to the substrate issmaller than that on the plane parallel to the substrate. Therefore,with use of the sputtering apparatus with the above structure, theinsulator 406 c can be formed on planes without planes perpendicular tothe substrate as illustrated in FIGS. 19C and 19D.

The perpendicular distance between the target 100 and the collimator 150and that between the substrate 160 and the collimator 150 may beappropriately changed in accordance with quality of a film which isformed. Thus, the collimator 150 may include a movable portion 151 and amovable portion 152 as illustrated in FIG. 22. By including the movableportion 151, whether the collimator 150 is used or not can be easilyselected. By including the movable portion 152, the perpendiculardistance between the collimator 150 and the substrate 160 and thatbetween the collimator 150 and the target 100 can be easily adjusted.

Alternatively, a long throw sputtering method can also be used. In thelong throw sputtering method, the perpendicular distance between thetarget 100 and the substrate 160 is set large, whereby the incidentdirection of the sputtered particle can be approximately perpendicularto the substrate 160. Accordingly, the insulator 406 c can be formed onplanes without planes perpendicular to the substrate even when thecollimator 150 is not used. Note that the perpendicular distance betweenthe substrate 160 and the target 100 is greater than or equal to 150 mmand less than or equal to 500 mm. Note that a combination of the longthrow sputtering method and the collimator 150 may be employed.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, as illustrated in FIGS. 19E and 19F, the insulator 406 d isformed. The insulator 406 d can be formed in the steps similar to thoseof the insulator 406 c.

Next, as illustrated in FIGS. 20A and 20B, the insulator to be theinsulator 412, the conductor to be the conductor 404 a, and theconductor to be the conductor 404 b are formed.

First, the insulator to be the insulator 412 is formed over theinsulator 410 and the insulator 406 d. The insulator to be the insulator412 can be formed by a sputtering method, a CVD method, an MBE method, aPLD method, an ALD method, or the like.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Next, a conductor to be the conductor 404 a and a conductor to be theconductor 404 b are formed. The conductor to be the conductor 404 a andthe conductor to be the conductor 404 b can be formed by a sputteringmethod, a CVD method, an MBE method, a PLD method, an ALD method, or thelike. The conductor to be the conductor 404 a and the conductor theconductor to be the conductor 404 b are formed so as to fill the openingformed in the insulator 410 and the like. Therefore, the CVD method (theMCVD method, in particular) is preferred. A stacked-layer film of aconductor formed by an ALD method or the like and a conductor formed bya CVD method is preferred in some cases to increase adhesion of theconductor formed by an MCVD method. For example, a stacked-layer filmwhere titanium nitride and tungsten are formed in this order may beused.

Next, as illustrated in FIGS. 20C and 20D, the conductor 404 a, theconductor 404 b, the insulator 412, the insulator 406 c, and theinsulator 406 d are removed to expose the insulator 410 by CMP treatmentor the like. Here, the insulator 410 can be used as a stopper layer andthe thickness of the insulator 410 is reduced in some cases. Therefore,the insulator 410 is set to have a sufficient thickness so that theconductor 404 a and the conductor 404 b have sufficiently low resistancein a completed transistor, whereby a plurality of transistors with smallvariation in characteristics can be manufactured.

Note that the CMP treatment may be performed only once or plural times.When the CMP treatment is performed plural times, it is preferable thatfirst polishing be performed at a high polishing rate and finalpolishing be performed at a low polishing rate. By performing polishingsteps with different polishing rates in combination, the planarity ofthe polished surface can be further increased.

Next, the conductor to be the conductor 420 is formed. Note that theconductor 420 may have a stacked-layer structure. The conductor to bethe conductor 420 can be formed by a sputtering method, a CVD method, anMBE method, a PLD method, an ALD method, or the like. Next, theconductor to be the conductor 420 is processed by a photolithographymethod or the like, so that the conductor 420 is formed.

Next, as illustrated in FIGS. 20E and 20F, the insulator 408 is formedover the insulator 410 and the conductor 420. The insulator 408 can beformed by a sputtering method, a CVD method, an MBE method, a PLDmethod, an ALD method, or the like. Aluminum oxide is preferably formedas the insulator 408 using plasma containing oxygen, so that oxygen inthe plasma can be added to the top surface of the insulator 410 asexcess oxygen (exO). Excess oxygen can be added to the insulator 408 bysupplying oxygen through the insulator 410. Here, the mixed regioncontaining a large amount of excess oxygen might be formed in theinterface between the insulator 408 and the insulator 410 and thevicinity of the interface.

Next, carbon, hydrogen, and the like may be released by performing thehigh-density-plasma treatment. In addition, in the case where thehigh-density-plasma treatment is performed in an oxygen atmosphere,organic compound such as hydrocarbon can be released from an object.

Furthermore, second heat treatment may be performed at any time afterthe formation of the insulator 408. By the second heat treatment, theexcess oxygen contained in the insulator 410 and the mixed region 414 ismoved to the semiconductor 406 b through the insulator 412, theinsulator 402, the insulator 406 d, the insulator 406 c, and theinsulator 406 a. Since excess oxygen is moved to the semiconductor 406 bas described above, defects (oxygen vacancies) in the semiconductor 406b can be reduced.

Note that the second heat treatment may be performed at a temperaturesuch that excess oxygen in the insulator 410 and the mixed region 414 isdiffused to the semiconductor 406 b. For example, the description of thefirst heat treatment may be referred to for the second heat treatment.The second heat treatment is preferably performed at a temperature lowerthan that of the first heat treatment. The second heat treatment ispreferably performed at a temperature lower than that of the first heattreatment by higher than or equal to 20 □C and lower than or equal to150 □C, preferably higher than or equal to 40 □C and lower than or equalto 100 □C. Accordingly, superfluous release of excess oxygen from theinsulator 402 or the like can be inhibited. Note that the second heattreatment is not necessarily performed when heating during formation ofthe films can work as heat treatment comparable to the second heattreatment.

Although not illustrated, an opening reaching the conductor 416 a and anopening reaching the conductor 416 b may be formed in the insulator 408and the insulator 410, and conductors serving as wirings may be formedin the openings. Alternatively, an opening reaching the conductor 404may be formed in the insulator 408, and a conductor serving as a wiringmay be formed in the opening.

Through the above steps, the transistor illustrated in FIGS. 10A to 10Ccan be manufactured.

In Embodiment 5, one embodiment of the present invention has beendescribed. Note that one embodiment of the present invention is notlimited to the above examples. That is, since various embodiments of thepresent invention are disclosed in this embodiment and otherembodiments, one embodiment of the present invention is not limited to aspecific embodiment. The example in which an oxide semiconductor is usedas a semiconductor has been described as one embodiment of the presentinvention; however, one embodiment of the present invention is notlimited thereto. Depending on cases or conditions, silicon, germanium,silicon germanium, silicon carbide, gallium arsenide, aluminum galliumarsenide, indium phosphide, gallium nitride, an organic semiconductor,or the like may be used in one embodiment of the present invention.

The structure and method described in this embodiment can be implementedby being combined as appropriate with any of the other structures andmethods described in the other embodiments.

Embodiment 6 <Transistor Structure 8>

A transistor having a structure different from that in FIGS. 10A to 10Cand a manufacturing method thereof will be described with reference toFIGS. 12A to 12C and FIGS. 13A and 13B. FIGS. 12A to 12C are a top viewand cross-sectional views of a semiconductor device of one embodiment ofthe present invention. FIG. 12A is the top view, and FIGS. 12B and 12Care the cross-sectional views taken along dashed-dotted lines A1-A2 andA3-A4 in FIG. 12A, respectively. Note that for simplification of thedrawing, some components are not illustrated in the top view in FIG.12A. FIGS. 13A and 13B are enlarged views of cross-sectional viewsillustrated in FIGS. 12B and 12C.

In the transistor in FIG. 12B, the angle θ between the side surface ofthe insulator 410 and a top surface of the conductor 416 a is greaterthan 0° and less than 90°, and the insulator 406 d is formed on the sidesurface of the insulator 410 with the insulator 406 c positionedtherebetween. The angle θ is preferably greater than or equal to 75 □Cand less than 90 □C, preferably greater than or equal to 80□□C and lessthan 90□□C, further preferably greater than or equal to 85 □C and lessthan 90 □C. The insulator 406 c and the insulator 406 d are formedthinner in a region overlapping with the side surface of the conductor404 with the insulator 412 interposed therebetween than in a regionoverlapping with the bottom surface of the conductor 404. For the othercomponents, the description of the transistor in FIGS. 10A to 10C isreferred to.

As long as t1 is greater than L1 and L1/t1 is less than 1, either one ofthe insulator 406 c and the insulator 406 d in a region covering theside surface of the insulator 410 may be formed thin. Furthermore, oneof the insulator 406 c and the insulator 406 d in a region covering theside surface of the insulator 410 may be formed, and the other is notnecessarily provided.

FIGS. 13A and 13B are each an enlarged view of an opening provided inthe insulator 410 of the transistor in this embodiment. The top surfaceof the insulator 406 d is approximately the same level as the topsurfaces of the conductor 416 a and the conductor 416 b. Note that thetop surface of the insulator 406 d is a surface that is close to theconductor 404 a in a region where the insulator 406 d overlaps with thebottom surfaces of the conductor 404 a and the conductor 404 b. Ideally,the top surface of the insulator 406 d is preferably the same level asthe top surfaces of the conductors 416 a and 416 b as illustrated inFIG. 13A.

It is preferable that the top surface of the insulator 406 c beapproximately the same level as the interface between the semiconductor406 b and the conductors 416 a and 416 b. Note that the top surface ofthe insulator 406 c is a surface that is close to the conductor 404 a ina region where the insulator 406 c overlaps with the bottom surfaces ofthe conductor 404 a and the conductor 404 b. Ideally, the top surface ofthe insulator 406 c is preferably the same level as the interfacebetween the semiconductor 406 b and the conductors 416 a and 416 b. Notethat the insulator 406 c should at least fills in an over-etched portionof the semiconductor 406 b; however, it is not limited thereto, the topsurface of the insulator 406 c may be above the interface between thesemiconductor 406 b and the conductors 416 a and 416 b as illustrated inFIG. 13B.

The transistor of this embodiment has a structure in which twoinsulators, the insulators 406 c and 406 d, are provided over thesemiconductor 406 b; however, it is not limited thereto, three or morestacked layers may also be provided.

<Method 8 for Manufacturing Transistor>

First, the steps up to the step illustrated in FIG. 18H described inEmbodiment 5 are performed.

Next, the side surface of the insulator 410 is formed so that the angleθ between the side surface of the insulator 410 and the top surface ofthe conductor 416 a is greater than 0° and less than 90°□ Then, theinsulator 406 c and the insulator 406 d are formed with use of the filmformation apparatus described in Embodiment 5. Here, for example, thesmaller the angle θ is, the higher the probability of deposition ofsputtered particles becomes, in which case the insulator 406 c and theinsulator 406 d are formed thick on the side surface of the insulator410. The insulator 406 c and the insulator 406 d are formed thin on theside surface of the insulator 410 as the angle θ gets larger. In such amanner, the thicknesses of the insulator 406 c and the insulator 406 dformed on the side surface of the insulator 410 can be adjusted by theangle θ□ That is, L1, which is the width of the offset region to beformed, can be reduced. Accordingly, t1 is greater than L1, and L1/t1 isless than 1.

The subsequent steps may be performed in a manner similar to the stepsillustrated in the method 1 for manufacturing the transistor describedin Embodiment 5.

Through the above steps, the transistor illustrated in FIGS. 12A to 12Ccan be manufactured.

The structure and method described in this embodiment can be implementedby being combined as appropriate with any of the other structures andmethods described in the other embodiments.

Embodiment 7 <Transistor Structures 9 and 10>

Transistors having structures different from that in FIGS. 10A to 10Cand a manufacturing method thereof will be described with reference toFIGS. 14A to 14C and FIGS. 15A to 15C. FIGS. 14A to 14C and FIGS. 15A to15C are top views and cross-sectional views of semiconductor devices ofone embodiment of the present invention.

The transistors illustrated in FIGS. 14A to 14C and FIGS. 15A to 15C aredescribed. Note that FIGS. 14A and 15A are top views. FIG. 14B is across-sectional view taken along dashed-dotted line A1-A2 in FIG. 14A.FIG. 14C is a cross-sectional view taken along dashed-dotted line A3-A4illustrated in FIG. 14A. Note that for simplification of the drawing,some components in the top view in FIG. 14A are not illustrated.

FIG. 15B is a cross-sectional view taken along dashed-dotted line A1-A2illustrated in FIG. 15A. FIG. 15C is a cross-sectional view taken alongdashed-dotted line A3-A4 illustrated in FIG. 15A. Note that forsimplification of the drawing, some components in the top view in FIG.15A are not illustrated.

In transistors in FIGS. 14A to 14C and FIGS. 15A to 15C, the insulator406 c 2 (the insulator 406 c in FIGS. 15B and 15C), the insulator 406 d2 (the insulator 406 d in FIGS. 15B and 15C), the insulator 412, theconductor 404 a, and the conductor 404 b are also formed on part ofregions of a top surface of the insulator 410. For the other components,the description of the transistor in FIGS. 10A to 10C or the transistorin FIGS. 12A to 12C is referred to.

In the transistors in FIGS. 14A to 14C and FIGS. 15A to 15C, part of theconductor 404 a and the conductor 404 b serving as a gate electrode mayfunction as a wiring. That is, part of the conductors 404 a and 404 bwhich is formed over the insulator 410 with the insulator 406 c 2 (theinsulator 406 c in FIGS. 15B and 15C), the insulator 406 d 2 (theinsulator 406 d in FIGS. 15B and 15C), and the insulator 412 positionedtherebetween correspond to the conductor 420 in the transistor structure1. That is, in the structure, t2 is the perpendicular distance betweenthe part of the conductor 404 a which is over the insulator 410 and theconductor 416 a or the conductor 416 b. Note that since the insulator406 c 2 (the insulator 406 c in FIGS. 15B and 15C), the insulator 406 d2 (the insulator 406 d in FIGS. 15B and 15C), the insulator 412, theconductor 404 a, and the conductor 404 b are formed at the same time,the insulator 406 c, the insulator 406 d 2 (the insulator 406 d in FIGS.15B and 15C), and the insulator 412 are positioned between the topsurface of the insulator 410 and part of the conductor 404 a which isformed over the insulator 410. Therefore, t2, the length of thesummation of the thicknesses of the insulator 410, the insulator 406 c 2(the insulator 406 c in FIGS. 15B and 15C), and the insulator 406 d 2(the insulator 406 d in FIGS. 15A and 15C), can be sufficiently large,so that parasitic capacitance can be reduced.

<Methods 9 and 10 for Manufacturing Transistor>

A method for manufacturing the transistor illustrated in FIGS. 14A to14C is described below.

First, the steps up to the step illustrated in FIG. 19F described inEmbodiment 5 are performed.

Next, the insulator 406 c, the insulator 406 d, the insulator 412, theconductor 404 a, and the conductor 404 b are formed by aphotolithography method or the like. With this structure, a conductorcorresponding to the conductor 420 in the transistor structure 1 can beformed at the same time using the conductor 404 a and the conductor 404b.

Next, the insulator 408 is formed.

Through the above steps, the transistor illustrated in FIGS. 14A to 14Ccan be manufactured.

In the transistor in FIGS. 15A to 15C, the insulator 406 c, theinsulator 406 d, the insulator 412, the conductor 404 a, and theconductor 404 b each having a desired shape are formed in steps similarto those of the transistor illustrated in FIGS. 12A to 12C. Then, theinsulator 406 c, the insulator 406 d, the insulator 412, the conductor404 a, and the conductor 404 b are formed by a photolithography method.With this structure, a conductor corresponding to the conductor 420 inthe transistor structure 1 can be formed using the conductor 404 a andthe conductor 404 b.

Through the above steps, the transistor illustrated in FIGS. 15A to 15Ccan be manufactured.

The structure and method described in this embodiment can be implementedby being combined as appropriate with any of the other structures andmethods described in the other embodiments.

Embodiment 8 <Transistor Structures 11 and 12>

Transistors having structures different from that in FIGS. 10A to 10Cand a manufacturing method thereof will be described with reference toFIGS. 16A to 16C and FIGS. 17A to 17C. FIGS. 16A to 16C and FIGS. 17A to17C are top views and cross-sectional views of semiconductor devices ofone embodiment of the present invention.

The transistors described in FIGS. 16A to 16C and FIGS. 17A to 17C aredescribed. Note that FIGS. 16A and 17A are top views. FIG. 16B is across-sectional view taken along dashed-dotted line A1-A2 in FIG. 16A.FIG. 16C is a cross-sectional view taken along dashed-dotted line A3-A4illustrated in FIG. 16A. Note that for simplification of the drawing,some components in the top view in FIG. 16A are not illustrated.

FIG. 17B is a cross-sectional view taken along dashed-dotted line A1-A2illustrated in FIG. 17A. FIG. 17C is a cross-sectional view taken alongdashed-dotted line A3-A4 illustrated in FIG. 17A. Note that forsimplification of the drawing, some components are not illustrated inthe top view in FIG. 17A.

In the transistors illustrated in FIGS. 16A to 16C and FIGS. 17A to 17C,the conductor 416 a and the conductor 416 b are formed only over thesemiconductor 406 b. For the other components, the description of thetransistor in FIGS. 10A to 10C or the transistor in FIGS. 12A to 12C isreferred to.

<Methods 11 and 12 for Manufacturing Transistor>

A method for manufacturing the transistor illustrated in FIGS. 16A to16C is described below.

First, the steps up to the step illustrated in FIGS. 18A and 18Bdescribed in Embodiment 5 are performed.

Then, the conductor 416 is formed after the insulator 406 a and thesemiconductor 406 b are formed. Then, a resist is formed over theconductor 416 by a photolithography method or the like, and firstetching is performed on the conductor 416 using the resist as a mask.Then, after the resist is removed, a second etching is performed usingthe conductor 416 as a mask. The second etching is performed on theinsulator 406 a and the semiconductor 406 b.

The following steps are similar to the steps after the step illustratedin FIGS. 18G and 18H. Through the above steps, the transistorillustrated in FIGS. 16A to 16C can be manufactured.

In the transistor illustrated in FIGS. 17A to 17C, the insulator 406 a,the semiconductor 406 b, and the conductor 416 are formed in a mannersimilar to that of the transistor illustrated in FIGS. 16A to 16C. Then,the transistor is preferably formed through the steps similar to thoseof the transistor illustrated in FIGS. 12A to 12C.

Through the above steps, the transistor illustrated in FIGS. 17A to 17Ccan be manufactured.

The structure and method described in this embodiment can be implementedby being combined as appropriate with any of the other structures andmethods described in the other embodiments.

Embodiment 9 <Deposition Apparatus>

The structure of a deposition apparatus including the above sputteringapparatus will be described below. A structure of a deposition apparatusthat hardly allows the entry of impurities into a film during depositionwill be described with reference to FIG. 23 and FIGS. 24A to 24C.

FIG. 23 is a top view schematically illustrating a single wafermulti-chamber deposition apparatus 1700. The deposition apparatus 1700includes an atmosphere-side substrate supply chamber 1701 including acassette port 1761 for holding a substrate and an alignment port 1762for performing alignment of a substrate, an atmosphere-side substratetransfer chamber 1702 through which a substrate is transferred from theatmosphere-side substrate supply chamber 1701, a load lock chamber 1703a where a substrate is carried and the pressure inside the chamber isswitched from atmospheric pressure to reduced pressure or from reducedpressure to atmospheric pressure, an unload lock chamber 1703 b where asubstrate is carried out and the pressure inside the chamber is switchedfrom reduced pressure to atmospheric pressure or from atmosphericpressure to reduced pressure, a transfer chamber 1704 through which asubstrate is transferred in a vacuum, a substrate-heating chamber 1705where a substrate is heated, and deposition chambers 1706 a, 1706 b, and1706 c. Note that the sputtering apparatus 101 can be used for all orpart of the deposition chambers 1706 a, 1706 b, and 1706 c.

Note that a plurality of cassette ports 1761 may be provided asillustrated in FIG. 23 (in FIG. 23, three cassette ports 1761 areprovided).

The atmosphere-side substrate transfer chamber 1702 is connected to theload lock chamber 1703 a and the unload lock chamber 1703 b, the loadlock chamber 1703 a and the unload lock chamber 1703 b are connected tothe transfer chamber 1704, and the transfer chamber 1704 is connected tothe substrate-heating chamber 1705 and the deposition chambers 1706 a,1706 b, and 1706 c.

Gate valves 1764 are provided for connecting portions between chambersso that the pressure in each chamber except the atmosphere-sidesubstrate supply chamber 1701 and the atmosphere-side substrate transferchamber 1702 can be independently controlled. Moreover, theatmosphere-side substrate transfer chamber 1702 includes a transferrobot 1763 a and the transfer chamber 1704 includes a transfer robot1763 b. With the transfer robots, a substrate can be transferred.

It is preferable that the substrate-heating chamber 1705 also serve as aplasma treatment chamber. In the deposition apparatus 1700, it ispossible to transfer a substrate without exposure to the air betweentreatment and treatment; therefore, adsorption of impurities in the airon a substrate can be suppressed. In addition, the order of deposition,heat treatment, or the like can be freely determined. Note that thestructures of the transfer chambers, the deposition chambers, the loadlock chambers, the unload lock chambers, and the substrate-heatingchambers are not limited to the above, and the structures thereof can beset as appropriate depending on the space for placement or the processconditions.

Next, FIG. 24A, FIG. 24B, and FIG. 24C are a cross-sectional view takenalong dashed-dotted line X1-X2, a cross-sectional view taken alongdashed-dotted line Y1-Y2, and a cross-sectional view taken alongdashed-dotted line Y2-Y3, respectively, in the deposition apparatus 1700illustrated in FIG. 23.

FIG. 24A is a cross section of the substrate-heating chamber 1705 andthe transfer chamber 1704, and the substrate-heating chamber 1705includes a plurality of heating stages 1765 which can hold a substrate.Note that although the number of heating stages 1765 illustrated in FIG.24A is seven, it is not limited thereto and may be greater than or equalto one and less than seven, or greater than or equal to eight. Byincreasing the number of the heating stages 1765, a plurality ofsubstrates can be subjected to heat treatment at the same time, whichleads to an increase in productivity. In addition, the substrate-heatingchamber 1705 is connected to a vacuum pump 1770 through a valve. As thevacuum pump 1770, a dry pump and a mechanical booster pump can be used,for example.

As the substrate-heating chamber 1705, a resistance heater may be usedfor heating, for example. Alternatively, heat conduction or heatradiation from a medium such as a heated gas may be used as the heatingmechanism. For example, rapid thermal annealing (RTA) such as gas rapidthermal annealing (GRTA) or lamp rapid thermal annealing (LRTA) can beused. The LRTA is a method for heating an object by radiation of light(an electromagnetic wave) emitted from a lamp such as a halogen lamp, ametal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressuresodium lamp, or a high-pressure mercury lamp. In the GRTA, heattreatment is performed using a high-temperature gas. An inert gas isused as the gas.

Moreover, the substrate-heating chamber 1705 is connected to a refiner1781 through a mass flow controller 1780. Note that although the massflow controller 1780 and the refiner 1781 can be provided for each of aplurality of kinds of gases, only one mass flow controller 1780 and onerefiner 1781 are provided for easy understanding. As the gas introducedto the substrate-heating chamber 1705, a gas whose dew point is −80° C.or lower, preferably −100° C. or lower can be used; for example, anoxygen gas, a nitrogen gas, and a rare gas (e.g., an argon gas) areused.

The transfer chamber 1704 includes the transfer robot 1763 b. Thetransfer robot 1763 b includes a plurality of movable portions and anarm for holding a substrate and can transfer a substrate to eachchamber. In addition, the transfer chamber 1704 is connected to thevacuum pump 1770 and a cryopump 1771 through valves. With such astructure, evacuation can be performed using the vacuum pump 1770 whenthe pressure inside the transfer chamber 1704 is in the range ofatmospheric pressure to low or medium vacuum (about 0.1 Pa to severalhundred Pa) and then, by switching the valves, evacuation can beperformed using the cryopump 1771 when the pressure inside the transferchamber 1704 is in the range of middle vacuum to high or ultra-highvacuum (0.1 Pa to 1×10⁻⁷ Pa).

Alternatively, two or more cryopumps 1771 may be connected in parallelto the transfer chamber 1704. With such a structure, even when one ofthe cryopumps is in regeneration, evacuation can be performed using anyof the other cryopumps. Note that the above regeneration refers totreatment for discharging molecules (or atoms) entrapped in thecryopump. When molecules (or atoms) are entrapped too much in acryopump, the evacuation capability of the cryopump is lowered;therefore, regeneration is performed regularly.

FIG. 24B is a cross section of the deposition chamber 1706 b, thetransfer chamber 1704, and the load lock chamber 1703 a.

Here, the details of each deposition chamber are described withreference to FIG. 24B. Note that the description on the sputteringapparatus 101 illustrated in FIG. 21 is referred to for the structure ofeach deposition chamber, and can be combined with the followingdescription as appropriate. The deposition chamber 1706 b illustrated inFIG. 24B includes the target 100, the substrate stage 170, and thecollimator 150 provided between the target and the substrate stage. Notethat here, a substrate is provided on the substrate stage 170. Althoughnot illustrated, the substrate stage 170 may include a substrate holdingmechanism which holds the substrate, a rear heater which heats thesubstrate from the back surface, or the like.

The deposition chamber 1706 b is connected to a mass flow controller1780 through a gas heating system 1782, and the gas heating system 1782is connected to a refiner 1781 through the mass flow controller 1780.With the gas heating system 1782, a deposition gas can be heated to atemperature higher than or equal to 40° C. and lower than or equal to400° C., preferably higher than or equal to 50° C. and lower than orequal to 200° C. Note that although the gas heating system 1782, themass flow controller 1780, and the refiner 1781 can be provided for eachof a plurality of kinds of gases, only one gas heating system 1782, onemass flow controller 1780, and one refiner 1781 are provided for easyunderstanding. As the deposition gas, a gas whose dew point is −80° C.or lower, preferably −100° C. or lower is preferably used.

Note that a parallel-plate-type sputtering apparatus or an ion beamsputtering apparatus may be provided in the deposition chamber 1706 b.

In the case where the refiner is provided near a gas inlet, the lengthof a pipe between the refiner 1781 and the deposition chamber 1706 b isless than or equal to 10 m, preferably less than or equal to 5 m, morepreferably less than or equal to 1 m. When the length of the pipe isless than or equal to 10 m, less than or equal to 5 m, or less than orequal to 1 m, the effect of the release of gas from the pipe can bereduced accordingly. As the pipe for the gas, a metal pipe the inside ofwhich is covered with iron fluoride, aluminum oxide, chromium oxide, orthe like can be used. With the above pipe, the amount of released gascontaining impurities is made small and the entry of impurities into thedeposition gas can be reduced as compared with a SUS316L-EP pipe, forexample. In addition, a high-performance ultra-compact metal gasketjoint (UPG joint) may be used as a joint of the pipe. A structure whereall the materials of the pipe are metals is preferable because theeffect of the generated released gas or the external leakage can bereduced as compared with a structure where resin or the like is used.

The deposition chamber 1706 b is connected to a turbo molecular pump1772 and a vacuum pump 1770 through valves. In addition, the depositionchamber 1706 b preferably includes a cryotrap.

The cryotrap 1751 is a mechanism which can adsorb a molecule (or anatom) having a relatively high melting point, such as water. The turbomolecular pump 1772 is capable of stably evacuating a large-sizedmolecule (or atom), needs low frequency of maintenance, and thus enableshigh productivity, whereas it has a low capability in evacuatinghydrogen and water. Hence, the cryotrap 1751 is connected to thedeposition chamber 1706 b so as to have a high capability in evacuatingwater or the like. The temperature of a refrigerator of the cryotrap1751 is set to be lower than or equal to 100 K, preferably lower than orequal to 80 K. In the case where the cryotrap 1751 includes a pluralityof refrigerators, it is preferable to set the temperature of eachrefrigerator at a different temperature because efficient evacuation ispossible. For example, the temperature of a first-stage refrigerator maybe set to be lower than or equal to 100 K and the temperature of asecond-stage refrigerator may be set to be lower than or equal to 20 K.

Note that the evacuation method of the deposition chamber 1706 b is notlimited to the above, and a structure similar to that in the evacuationmethod described in the transfer chamber 1704 (the evacuation methodusing the cryopump and the vacuum pump) may be employed. Needless tosay, the evacuation method of the transfer chamber 1704 may have astructure similar to that of the deposition chamber 1706 b (theevacuation method using the turbo molecular pump and the vacuum pump).

Note that in each of the transfer chamber 1704, the substrate-heatingchamber 1705, and the deposition chamber 1706 b which are describedabove, the back pressure (total pressure) and the partial pressure ofeach gas molecule (atom) are preferably set as follows. In particular,the back pressure and the partial pressure of each gas molecule (atom)in the deposition chamber 1706 b need to be noted because impuritiesmight enter a film to be formed.

In each of the above chambers, the back pressure (total pressure) isless than or equal to 1×10⁻⁴ Pa, preferably less than or equal to 3×10⁻⁵Pa, more preferably less than or equal to 1×10⁻⁵ Pa. In each of theabove chambers, the partial pressure of a gas molecule (atom) having amass-to-charge ratio (m/z) of 18 is less than or equal to 3×10⁻⁵ Pa,preferably less than or equal to 1×10⁻⁵ Pa, more preferably less than orequal to 3×10⁻⁶ Pa. Moreover, in each of the above chambers, the partialpressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of28 is less than or equal to 3×10⁻⁵ Pa, preferably less than or equal to1×10⁻⁵ Pa, more preferably less than or equal to 3×10⁻⁶ Pa. Furthermore,in each of the above chambers, the partial pressure of a gas molecule(atom) having a mass-to-charge ratio (m/z) of 44 is less than or equalto 3×10⁻⁵ Pa, preferably less than or equal to 1×10⁻⁵ Pa, morepreferably less than or equal to 3×10⁻⁶ Pa.

Note that a total pressure and a partial pressure in a vacuum chambercan be measured using a mass analyzer. For example, Qulee CGM-051, aquadrupole mass analyzer (also referred to as Q-mass) manufactured byULVAC, Inc. may be used.

Moreover, the transfer chamber 1704, the substrate-heating chamber 1705,and the deposition chamber 1706 b, which are described above, preferablyhave a small amount of external leakage or internal leakage.

For example, in each of the transfer chamber 1704, the substrate-heatingchamber 1705, and the deposition chamber 1706 b which are describedabove, the leakage rate is less than or equal to 3×10⁻⁶ Pa·m³/s,preferably less than or equal to 1×10⁻⁶ Pa·m³/s. The leakage rate of agas molecule (atom) having a mass-to-charge ratio (m/z) of 18 is lessthan or equal to 1×10⁻⁷ Pa·m³/s, preferably less than or equal to 3×10⁻⁸Pa·m³/s. The leakage rate of a gas molecule (atom) having amass-to-charge ratio (m/z) of 28 is less than or equal to 1×10⁻⁵Pa·m³/s, preferably less than or equal to 1×10⁻⁶ Pa·m³/s. The leakagerate of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 44is less than or equal to 3×10⁻⁶ Pa·m³/s, preferably less than or equalto 1×10⁻⁶ Pa·m³/s.

Note that a leakage rate can be derived from the total pressure andpartial pressure measured using the mass analyzer.

The leakage rate depends on external leakage and internal leakage. Theexternal leakage refers to inflow of gas from the outside of a vacuumsystem through a minute hole, a sealing defect, or the like. Theinternal leakage is due to leakage through a partition, such as a valve,in a vacuum system or due to released gas from an internal member.Measures need to be taken from both aspects of external leakage andinternal leakage in order that the leakage rate is set to be less thanor equal to the above value.

For example, an open/close portion of the deposition chamber 1706 b canbe sealed with a metal gasket. For the metal gasket, metal covered withiron fluoride, aluminum oxide, or chromium oxide is preferably used. Themetal gasket realizes higher adhesion than an O-ring, and can reduce theexternal leakage. Furthermore, with the use of the metal covered withiron fluoride, aluminum oxide, chromium oxide, or the like, which is inthe passive state, the release of gas containing impurities releasedfrom the metal gasket is suppressed, so that the internal leakage can bereduced.

For a member of the deposition apparatus 1700, aluminum, chromium,titanium, zirconium, nickel, or vanadium, which releases a smalleramount of gas containing impurities, is used. Alternatively, for theabove member, an alloy containing iron, chromium, nickel, and the likecovered with the above material may be used. The alloy containing iron,chromium, nickel, and the like is rigid, resistant to heat, and suitablefor processing. Here, when surface unevenness of the member is decreasedby polishing or the like to reduce the surface area, the release of gascan be reduced.

Alternatively, the above member of the deposition apparatus 1700 may becovered with iron fluoride, aluminum oxide, chromium oxide, or the like.

The member of the deposition apparatus 1700 is preferably formed withonly metal as much as possible. For example, in the case where a viewingwindow formed with quartz or the like is provided, it is preferable thatthe surface of the viewing window be thinly covered with iron fluoride,aluminum oxide, chromium oxide, or the like so as to suppress release ofgas.

When an adsorbed substance is present in the deposition chamber, theadsorbed substance does not affect the pressure in the depositionchamber because it is adsorbed onto an inner wall or the like; however,the adsorbed substance causes gas to be released when the inside of thedeposition chamber is evacuated. Therefore, although there is nocorrelation between the leakage rate and the evacuation rate, it isimportant that the adsorbed substance present in the deposition chamberbe desorbed as much as possible and evacuation be performed in advancewith the use of a pump with high evacuation capability. Note that thedeposition chamber may be subjected to baking to promote desorption ofthe adsorbed substance. By the baking, the desorption rate of theadsorbed substance can be increased about tenfold. The baking can beperformed at a temperature in the range of 100° C. to 450° C. At thistime, when the adsorbed substance is removed while an inert gas isintroduced to the deposition chamber, the desorption rate of water orthe like, which is difficult to be desorbed simply by evacuation, can befurther increased. Note that when the inert gas is heated tosubstantially the same temperature as the baking temperature of thedeposition chamber, the desorption rate of the adsorbed substance can befurther increased. Here, a rare gas is preferably used as an inert gas.Depending on the kind of a film to be deposited, oxygen or the like maybe used instead of an inert gas. For example, in the case of depositingan oxide, the use of oxygen which is the main component of the oxide ispreferable in some cases.

Alternatively, treatment for evacuating the inside of the depositionchamber is preferably performed a certain period of time after heatedoxygen, a heated inert gas such as a heated rare gas, or the like isused to increase a pressure in the deposition chamber. The heated gascan desorb the adsorbed substance in the deposition chamber, and theimpurities present in the deposition chamber can be reduced. Note thatan advantageous effect can be achieved when this treatment is repeatedmore than or equal to 2 times and less than or equal to 30 times,preferably more than or equal to 5 times and less than or equal to 15times. Specifically, an inert gas, oxygen, or the like with atemperature higher than or equal to 40° C. and lower than or equal to400° C., preferably higher than or equal to 50° C. and lower than orequal to 200° C. is introduced to the deposition chamber, so that thepressure therein can be kept to be greater than or equal to 0.1 Pa andless than or equal to 10 kPa, preferably greater than or equal to 1 Paand less than or equal to 1 kPa, more preferably greater than or equalto 5 Pa and less than or equal to 100 Pa in the time range of 1 minuteto 300 minutes, preferably 5 minutes to 120 minutes. After that, theinside of the deposition chamber is evacuated in the time range of 5minutes to 300 minutes, preferably 10 minutes to 120 minutes.

The desorption rate of the adsorbed substance can be further increasedalso by dummy deposition. Here, the dummy deposition refers todeposition on a dummy substrate by a sputtering method or the like, inwhich a film is deposited on the dummy substrate and the inner wall ofthe deposition chamber so that impurities in the deposition chamber andan adsorbed substance on the inner wall of the deposition chamber areconfined in the film. For a dummy substrate, a substrate which releasesa smaller amount of gas is preferably used. By performing dummydeposition, the concentration of impurities in a film which will bedeposited later can be reduced. Note that the dummy deposition may beperformed at the same time as the baking of the deposition chamber.

Next, the details of the transfer chamber 1704 and the load lock chamber1703 a illustrated in FIG. 24B and the atmosphere-side substratetransfer chamber 1702 and the atmosphere-side substrate supply chamber1701 illustrated in FIG. 24C are described. Note that FIG. 24C is across section of the atmosphere-side substrate transfer chamber 1702 andthe atmosphere-side substrate supply chamber 1701.

For the transfer chamber 1704 illustrated in FIG. 24B, the descriptionof the transfer chamber 1704 illustrated in FIG. 24A can be referred to.

The load lock chamber 1703 a includes a substrate delivery stage 1752.When a pressure in the load lock chamber 1703 a becomes atmosphericpressure by being increased from reduced pressure, the substratedelivery stage 1752 receives a substrate from the transfer robot 1763 aprovided in the atmosphere-side substrate transfer chamber 1702. Afterthat, the load lock chamber 1703 a is evacuated into vacuum so that thepressure therein becomes reduced pressure and then the transfer robot1763 b provided in the transfer chamber 1704 receives the substrate fromthe substrate delivery stage 1752.

Furthermore, the load lock chamber 1703 a is connected to the vacuumpump 1770 and the cryopump 1771 through valves. For a method forconnecting evacuation systems such as the vacuum pump 1770 and thecryopump 1771, the description of the method for connecting the transferchamber 1704 can be referred to, and the description thereof is omittedhere. Note that the unload lock chamber 1703 b illustrated in FIG. 23can have a structure similar to that in the load lock chamber 1703 a.

The atmosphere-side substrate transfer chamber 1702 includes thetransfer robot 1763 a. The transfer robot 1763 a can deliver a substratefrom the cassette port 1761 to the load lock chamber 1703 a or deliver asubstrate from the load lock chamber 1703 a to the cassette port 1761.Furthermore, a mechanism for suppressing entry of dust or a particle,such as high efficiency particulate air (HEPA) filter, may be providedabove the atmosphere-side substrate transfer chamber 1702 and theatmosphere-side substrate supply chamber 1701.

The atmosphere-side substrate supply chamber 1701 includes a pluralityof cassette ports 1761. The cassette port 1761 can hold a plurality ofsubstrates.

The surface temperature of the target is set to be lower than or equalto 100° C., preferably lower than or equal to 50° C., more preferablyabout room temperature (typically, 25° C.). In a sputtering apparatusfor a large substrate, a large target is often used. However, it isdifficult to form a target for a large substrate without a juncture. Infact, a plurality of targets is arranged so that there is as littlespace as possible therebetween to obtain a large shape; however, aslight space is inevitably generated. When the surface temperature ofthe target increases, in some cases, zinc or the like is volatilizedfrom such a slight space and the space might be expanded gradually. Whenthe space expands, a metal of a backing plate or a metal used foradhesion might be sputtered and might cause an increase in impurityconcentration. Thus, it is preferable that the target be cooledsufficiently.

Specifically, for the backing plate, a metal having high conductivityand a high heat dissipation property (specifically copper) is used. Thetarget can be cooled efficiently by making a sufficient amount ofcooling water flow through a water channel which is formed in thebacking plate.

Note that in the case where the target contains zinc, plasma damage isalleviated by the deposition in an oxygen gas atmosphere; thus, an oxidesemiconductor in which zinc is unlikely to be volatilized can beobtained.

With the above deposition apparatus, entry of impurities into the filmto be formed can be suppressed.

Embodiment 10 <Manufacturing Apparatus>

A manufacturing apparatus which performs high-density plasma treatmentaccording to one embodiment of the present invention will be describedbelow.

First, a structure of a manufacturing apparatus which hardly allowsentry of impurities in manufacturing a semiconductor device or the likeis described with reference to FIG. 25, FIG. 26, and FIG. 27.

FIG. 25 is a top view schematically illustrating a single wafermulti-chamber manufacturing apparatus 2700. The manufacturing apparatus2700 includes an atmosphere-side substrate supply chamber 2701 includinga cassette port 2761 for holding a substrate and an alignment port 2762for performing alignment of a substrate, an atmosphere-side substratetransfer chamber 2702 through which a substrate is transferred from theatmosphere-side substrate supply chamber 2701, a load lock chamber 2703a where a substrate is carried and the pressure inside the chamber isswitched from atmospheric pressure to reduced pressure or from reducedpressure to atmospheric pressure, an unload lock chamber 2703 b where asubstrate is carried out and the pressure inside the chamber is switchedfrom reduced pressure to atmospheric pressure or from atmosphericpressure to reduced pressure, a transfer chamber 2704 through which asubstrate is transferred in a vacuum, and chambers 2706 a, 2706 b, 2706c, and 2706 d.

The atmosphere-side substrate transfer chamber 2702 is connected to theload lock chamber 2703 a and the unload lock chamber 2703 b, the loadlock chamber 2703 a and the unload lock chamber 2703 b are connected tothe transfer chamber 2704, and the transfer chamber 2704 is connected tothe chambers 2706 a, 2706 b, 2706 c, and 2706 d.

Note that gate valves GV are provided in connecting portions between thechambers so that each chamber excluding the atmosphere-side substratesupply chamber 2701 and the atmosphere-side substrate transfer chamber2702 can be independently kept in a vacuum state. In addition, theatmosphere-side substrate transfer chamber 2702 is provided with atransfer robot 2763 a, and the transfer chamber 2704 is provided with atransfer robot 2763 b. With the transfer robot 2763 a and the transferrobot 2763 b, a substrate can be transferred inside the manufacturingapparatus 2700.

In the transfer chamber 2704 and each of the chambers 2706 a to 2706 d,the back pressure (total pressure) is, for example, lower than or equalto 1×10⁻⁴ Pa, preferably lower than or equal to 3×10⁻⁵ Pa, furtherpreferably lower than or equal to 1×10⁻⁵ Pa. In the transfer chamber2704 and each of the chambers 2706 a to 2706 d, the partial pressure ofa gas molecule (atom) having a mass-to-charge ratio (m/z) of 18 is, forexample, lower than or equal to 3×10⁻⁵ Pa, preferably lower than orequal to 1×10⁻⁵ Pa, further preferably lower than or equal to 3×10⁻⁶ Pa.Moreover, in the transfer chamber 2704 and each of the chambers 2706 ato 2706 d, the partial pressure of a gas molecule (atom) having amass-to-charge ratio (m/z) of 28 is, for example, lower than or equal to3×10⁻⁵ Pa, preferably lower than or equal to 1×10⁻⁵ Pa, furtherpreferably lower than or equal to 3×10⁻⁶ Pa. Further, in the transferchamber 2704 and each of the chambers 2706 a to 2706 d, the partialpressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of44 is, for example, lower than or equal to 3×10⁻⁵ Pa, preferably lowerthan or equal to 1×10⁻⁵ Pa, further preferably lower than or equal to3×10⁻⁶ Pa.

Note that the total pressure and the partial pressure in the transferchamber 2704 and each of the chambers 2706 a to 2706 d can be measuredusing a mass analyzer. For example, Qulee CGM-051, a quadrupole massanalyzer (also referred to as Q-mass) manufactured by ULVAC, Inc. can beused.

Moreover, the transfer chamber 2704 and each of the chambers 2706 a to2706 d preferably have a small amount of external leakage or internalleakage. For example, in the transfer chamber 2704 and each of thechambers 2706 a to 2706 d, the leakage rate is less than or equal to3×10⁻⁶ Pa·m³/s, preferably less than or equal to 1×10⁻⁶ Pa·m³/s. Forexample, the leakage rate of a gas molecule (atom) having amass-to-charge ratio (m/z) of 18 is less than or equal to 1×10⁻⁷Pa·m³/s, preferably less than or equal to 3×10⁻⁸ Pa·m³/s. For example,the leakage rate of a gas molecule (atom) having a mass-to-charge ratio(m/z) of 28 is less than or equal to 1×10⁻⁵ Pa·m³/s, preferably lessthan or equal to 1×10⁻⁶ Pa·m³/s. For example, the leakage rate of a gasmolecule (atom) having a mass-to-charge ratio (m/z) of 44 is less thanor equal to 3×10⁻⁶ Pa·m³/s, preferably less than or equal to 1×10⁻⁶Pa·m³/s.

Note that a leakage rate can be derived from the total pressure andpartial pressure measured using the mass analyzer. The leakage ratedepends on external leakage and internal leakage. The external leakagerefers to inflow of gas from the outside of a vacuum system through aminute hole, a sealing defect, or the like. The internal leakage is dueto leakage through a partition, such as a valve, in a vacuum system ordue to released gas from an internal member. Measures need to be takenfrom both aspects of external leakage and internal leakage in order thatthe leakage rate can be set to be less than or equal to theabove-mentioned value.

For example, open/close portions of the transfer chamber 2704 and thechambers 2706 a to 2706 d can be sealed with a metal gasket. For themetal gasket, metal covered with iron fluoride, aluminum oxide, orchromium oxide is preferably used. The metal gasket realizes higheradhesion than an O-ring, and can reduce the external leakage.Furthermore, with the use of the metal covered with iron fluoride,aluminum oxide, chromium oxide, or the like, which is in the passivestate, the release of gas containing impurities released from the metalgasket is suppressed, so that the internal leakage can be reduced.

For a member of the manufacturing apparatus 2700, aluminum, chromium,titanium, zirconium, nickel, or vanadium, which releases a small amountof gas containing impurities, is used. Alternatively, an alloycontaining iron, chromium, nickel, or the like covered with the abovematerial may be used. The alloy containing iron, chromium, nickel, orthe like is rigid, resistant to heat, and suitable for processing. Here,when surface unevenness of the member is decreased by polishing or thelike to reduce the surface area, the release of gas can be reduced.

Alternatively, the above member of the manufacturing apparatus 2700 maybe covered with iron fluoride, aluminum oxide, chromium oxide, or thelike.

The member of the manufacturing apparatus 2700 is preferably formedusing only metal when possible. For example, in the case where a viewingwindow formed of quartz or the like is provided, it is preferable thatthe surface of the viewing window be thinly covered with iron fluoride,aluminum oxide, chromium oxide, or the like so as to suppress release ofgas.

When an adsorbed substance is present in the transfer chamber 2704 andeach of the chambers 2706 a to 2706 d, although the adsorbed substancedoes not affect the pressure in the transfer chamber 2704 and each ofthe chambers 2706 a to 2706 d because it is adsorbed onto an inner wallor the like, the adsorbed substance causes a release of gas when theinside of the transfer chamber 2704 and each of the chambers 2706 a to2706 d is evacuated. Therefore, although there is no correlation betweenthe leakage rate and the exhaust rate, it is important that the adsorbedsubstance present in the transfer chamber 2704 and each of the chambers2706 a to 2706 d be desorbed as much as possible and exhaust beperformed in advance with the use of a pump with high exhaustcapability. Note that the transfer chamber 2704 and each of the chambers2706 a to 2706 d may be subjected to baking to promote desorption of theadsorbed substance. By the baking, the desorption rate of the adsorbedsubstance can be increased about tenfold. The baking can be performed ata temperature of higher than or equal to 100° C. and lower than or equalto 450° C. At this time, when the adsorbed substance is removed while aninert gas is introduced into the transfer chamber 2704 and each of thechambers 2706 a to 2706 d, the desorption rate of water or the like,which is difficult to desorb simply by exhaust, can be furtherincreased. Note that when the inert gas that is introduced is heated tosubstantially the same temperature as the baking temperature, thedesorption rate of the adsorbed substance can be further increased.Here, a rare gas is preferably used as the inert gas.

Alternatively, treatment for evacuating the inside of the transferchamber 2704 and each of the chambers 2706 a to 2706 d is preferablyperformed a certain period of time after heated oxygen, a heated inertgas such as a heated rare gas, or the like is introduced to increase thepressure in the transfer chamber 2704 and each of the chambers 2706 a to2706 d. The introduction of the heated gas can desorb the adsorbedsubstance in the transfer chamber 2704 and each of the chambers 2706 ato 2706 d, and the impurities present in the transfer chamber 2704 andeach of the chambers 2706 a to 2706 d can be reduced. Note that anadvantageous effect can be achieved when this treatment is repeated morethan or equal to 2 times and less than or equal to 30 times, preferablymore than or equal to 5 times and less than or equal to 15 times.Specifically, an inert gas, oxygen, or the like with a temperaturehigher than or equal to 40° C. and lower than or equal to 400° C.,preferably higher than or equal to 50° C. and lower than or equal to200° C. is introduced to the transfer chamber 2704 and each of thechambers 2706 a to 2706 d, so that the pressure therein can be kept tobe higher than or equal to 0.1 Pa and lower than or equal to 10 kPa,preferably higher than or equal to 1 Pa and lower than or equal to 1kPa, further preferably higher than or equal to 5 Pa and lower than orequal to 100 Pa in the time range of 1 minute to 300 minutes, preferably5 minutes to 120 minutes. After that, the inside of the transfer chamber2704 and each of the chambers 2706 a to 2706 d is evacuated in the timerange of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

Next, the chambers 2706 b and 2706 c are described with reference to aschematic cross-sectional view of FIG. 26.

The chambers 2706 b and 2706 c are chambers capable of performinghigh-density plasma treatment on an object, for example. Because thechambers 2706 b and 2706 c have a common structure with the exception ofthe atmosphere used in the high-density plasma treatment, they arecollectively described below.

The chambers 2706 b and 2706 c each include a slot antenna plate 2808, adielectric plate 2809, a substrate stage 2812, and an exhaust port 2819.A gas supply source 2801, a valve 2802, a high-frequency generator 2803,a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide2807, a matching box 2815, a high-frequency power source 2816, a vacuumpump 2817, and a valve 2818 are provided outside the chambers 2706 b and2706 c.

The high-frequency generator 2803 is connected to the mode converter2805 through the waveguide 2804. The mode converter 2805 is connected tothe slot antenna plate 2808 through the waveguide 2807. The slot antennaplate 2808 is positioned in contact with the dielectric plate 2809.Further, the gas supply source 2801 is connected to the mode converter2805 through the valve 2802. Gas is transferred to the chambers 2706 band 2706 c through the gas pipe 2806 which runs through the modeconverter 2805, the waveguide 2807, and the dielectric plate 2809. Thevacuum pump 2817 has a function of exhausting gas or the like from thechambers 2706 b and 2706 c through the valve 2818 and the exhaust port2819. The high-frequency power source 2816 is connected to the substratestage 2812 through the matching box 2815.

The substrate stage 2812 has a function of holding a substrate 2811. Forexample, the substrate stage 2812 has a function of holding thesubstrate 2811 by static electricity or mechanical strength. Inaddition, the substrate stage 2812 has a function of an electrode towhich electric power is supplied from the high-frequency power source2816. The substrate stage 2812 includes a heating mechanism 2813 thereinand thus has a function of heating the substrate 2811.

As the vacuum pump 2817, a dry pump, a mechanical booster pump, an ionpump, a titanium sublimation pump, a cryopump, a turbomolecular pump, orthe like can be used, for example. In addition to the vacuum pump 2817,a cryotrap may be used as well. The combinational use of the cryopumpand the cryotrap allows water to be efficiently exhausted and isparticularly preferable.

For example, the heating mechanism 2813 may be a heating mechanism whichuses a resistance heater or the like for heating. Alternatively, aheating mechanism which utilizes heat conduction or heat radiation froma medium such as a heated gas for heating may be used. For example, RTAsuch as GRTA or LRTA can be used. In GRTA, heat treatment is performedusing a high-temperature gas. An inert gas is used as the gas.

The gas supply source 2801 may be connected to a purifier through a massflow controller. As the gas, a gas whose dew point is −80° C. or lower,preferably −100° C. or lower is preferably used. For example, an oxygengas, a nitrogen gas, or a rare gas (e.g., an argon gas) may be used.

As the dielectric plate 2809, silicon oxide (quartz), aluminum oxide(alumina), yttrium oxide (yttria), or the like may be used, for example.A protective layer may be further formed on a surface of the dielectricplate 2809. As the protective layer, magnesium oxide, titanium oxide,chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, siliconoxide, aluminum oxide, yttrium oxide, or the like may be used. Thedielectric plate 2809 is exposed to an especially high density region ofhigh-density plasma 2810 that is to be described later. Therefore, theprotective layer can reduce the damage and consequently prevent anincrease of particles or the like during the treatment.

The high-frequency generator 2803 has a function of generating amicrowave with a frequency of, for example, more than or equal to 0.3GHz and less than or equal to 3.0 GHz, more than or equal to 0.7 GHz andless than or equal to 1.1 GHz, or more than or equal to 2.2 GHz and lessthan or equal to 2.8 GHz. The microwave generated by the high-frequencygenerator 2803 is propagated to the mode converter 2805 through thewaveguide 2804. The mode converter 2805 converts the microwavepropagated in the TE mode into a microwave in the TEM mode. Then, themicrowave is propagated to the slot antenna plate 2808 through thewaveguide 2807. The slot antenna plate 2808 is provided with a pluralityof slot holes, and the microwave propagates through the slot holes andthe dielectric plate 2809. Then, an electric field is generated belowthe dielectric plate 2809, and the high-density plasma 2810 can begenerated. The high-density plasma 2810 includes ions and radicalsdepending on the gas species supplied from the gas supply source 2801.For example, oxygen radicals, nitrogen radicals, or the like areincluded.

At this time, the quality of a film or the like over the substrate 2811can be modified by the ions and radicals generated in the high-densityplasma 2810. Note that it is preferable in some cases to apply a bias tothe substrate 2811 using the high-frequency power source 2816. As thehigh-frequency power source 2816, a radio frequency (RF) power sourcewith a frequency of 13.56 MHz, 27.12 MHz, or the like may be used, forexample. The application of a bias to the substrate allows ions in thehigh-density plasma 2810 to efficiently reach a deep portion of anopening of the film or the like over the substrate 2811.

For example, in the chamber 2706 b, oxygen radical treatment using thehigh-density plasma 2810 can be performed by introducing oxygen from thegas supply source 2801. In the chamber 2706 c, nitrogen radicaltreatment using the high-density plasma 2810 can be performed byintroducing nitrogen from the gas supply source 2801.

Next, the chambers 2706 a and 2706 d are described with reference to aschematic cross-sectional view of FIG. 27.

The chambers 2706 a and 2706 d are chambers capable of irradiating anobject with an electromagnetic wave, for example. Because the chambers2706 a and 2706 d have a common structure with the exception of the kindof the electromagnetic wave, they are collectively described below.

The chambers 2706 a and 2706 d each include one or more lamps 2820, asubstrate stage 2825, a gas inlet 2823, and an exhaust port 2830. A gassupply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829are provided outside the chambers 2706 a and 2706 d.

The gas supply source 2821 is connected to the gas inlet 2823 throughthe valve 2822. The vacuum pump 2828 is connected to the exhaust port2830 through the valve 2829. The lamp 2820 is provided to face thesubstrate stage 2825. The substrate stage 2825 has a function of holdinga substrate 2824. The substrate stage 2825 includes a heating mechanism2826 therein and thus has a function of heating the substrate 2824.

As the lamp 2820, a light source having a function of emitting anelectromagnetic wave such as visible light or ultraviolet light may beused, for example. For example, a light source having a function ofemitting an electromagnetic wave which has a peak in a wavelength regionof longer than or equal to 10 nm and shorter than or equal to 2500 nm,longer than or equal to 500 nm and shorter than or equal to 2000 nm, orlonger than or equal to 40 nm and shorter than or equal to 340 nm may beused.

As the lamp 2820, a light source such as a halogen lamp, a metal halidelamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp,or a high-pressure mercury lamp may be used, for example.

For example, part of or the whole electromagnetic wave emitted from thelamp 2820 is absorbed by the substrate 2824, so that the quality of afilm or the like over the substrate 2824 can be modified. For example,defects can be generated or reduced or impurities can be removed. Whenthe lamp 2820 radiates the electromagnetic wave while the substrate 2824is heated, generation or reduction of defects or removal of impuritiescan be efficiently performed.

Alternatively, for example, the electromagnetic wave emitted from thelamp 2820 may cause heat generation in the substrate stage 2825, bywhich the substrate 2824 may be heated. In this case, the heatingmechanism 2826 inside the substrate stage 2825 may be omitted.

For the vacuum pump 2828, the description of the vacuum pump 2817 isreferred to. For the heating mechanism 2826, the description of theheating mechanism 2813 is referred to. For the gas supply source 2821,the description of the gas supply source 2801 is referred to.

With the above-described manufacturing apparatus, the quality of a filmcan be modified while the entry of impurities into an object suppressed.

The structure and method described in this embodiment can be implementedby being combined as appropriate with any of the other structures andmethods described in the other embodiments.

Embodiment 11 <Structure of Oxide Semiconductor>

A structure of an oxide semiconductor will be described below.

An oxide semiconductor is classified into a single crystal oxidesemiconductor and a non-single-crystal oxide semiconductor. Examples ofa non-single-crystal oxide semiconductor include a c-axis alignedcrystalline oxide semiconductor (CAAC-OS), a polycrystalline oxidesemiconductor, a nanocrystalline oxide semiconductor (nc-OS), anamorphous-like oxide semiconductor (a-like OS), and an amorphous oxidesemiconductor.

From another perspective, an oxide semiconductor is classified into anamorphous oxide semiconductor and a crystalline oxide semiconductor.Examples of a crystalline oxide semiconductor include a single crystaloxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor,and an nc-OS.

It is known that an amorphous structure is generally defined as beingmetastable and unfixed, and being isotropic and having no non-uniformstructure. In other words, an amorphous structure has a flexible bondangle and a short-range order but does not have a long-range order.

This means that an inherently stable oxide semiconductor cannot beregarded as a completely amorphous oxide semiconductor. Moreover, anoxide semiconductor that is not isotropic (e.g., an oxide semiconductorthat has a periodic structure in a microscopic region) cannot beregarded as a completely amorphous oxide semiconductor. Note that ana-like OS has a periodic structure in a microscopic region, but at thesame time has a void and has an unstable structure. For this reason, ana-like OS has physical properties similar to those of an amorphous oxidesemiconductor.

<CAAC-OS>

First, a CAAC-OS is described.

A CAAC-OS is one of oxide semiconductors having a plurality of c-axisaligned crystal parts (also referred to as pellets).

In a combined analysis image (also referred to as a high-resolution TEMimage) of a bright-field image and a diffraction pattern of a CAAC-OS,which is obtained using a transmission electron microscope (TEM), aplurality of pellets can be observed. However, in the high-resolutionTEM image, a boundary between pellets, that is, a grain boundary is notclearly observed. Thus, in the CAAC-OS, a reduction in electron mobilitydue to the grain boundary is less likely to occur.

A CAAC-OS observed with TEM is described below. FIG. 28A shows ahigh-resolution TEM image of a cross section of the CAAC-OS which isobserved from a direction substantially parallel to the sample surface.The high-resolution TEM image is obtained with a spherical aberrationcorrector function. The high-resolution TEM image obtained with aspherical aberration corrector function is particularly referred to as aCs-corrected high-resolution TEM image. The Cs-corrected high-resolutionTEM image can be obtained with, for example, an atomic resolutionanalytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 28B is an enlarged Cs-corrected high-resolution TEM image of aregion (1) in FIG. 28A. FIG. 28B shows that metal atoms are arranged ina layered manner in a pellet. Each metal atom layer has a configurationreflecting unevenness of a surface over which the CAAC-OS is formed(hereinafter, the surface is referred to as a formation surface) or thetop surface of the CAAC-OS, and is arranged parallel to the formationsurface or the top surface of the CAAC-OS.

As shown in FIG. 28B, the CAAC-OS has a characteristic atomicarrangement. The characteristic atomic arrangement is denoted by anauxiliary line in FIG. 28C. FIGS. 28B and 28C prove that the size of apellet is greater than or equal to 1 nm or greater than or equal to 3nm, and the size of a space caused by tilt of the pellets isapproximately 0.8 nm. Therefore, the pellet can also be referred to as ananocrystal (nc). Furthermore, the CAAC-OS can also be referred to as anoxide semiconductor including c-axis aligned nanocrystals (CANC).

Here, according to the Cs-corrected high-resolution TEM images, theschematic arrangement of pellets 5100 of a CAAC-OS over a substrate 5120is illustrated by such a structure in which bricks or blocks are stacked(see FIG. 28D). The part in which the pellets are tilted as observed inFIG. 28C corresponds to a region 5161 shown in FIG. 28D.

FIG. 29A shows a Cs-corrected high-resolution TEM image of a plane ofthe CAAC-OS observed from a direction substantially perpendicular to thesample surface. FIGS. 29B, 29C, and 29D are enlarged Cs-correctedhigh-resolution TEM images of regions (1), (2), and (3) in FIG. 29A,respectively. FIGS. 29B, 29C, and 29D indicate that metal atoms arearranged in a triangular, quadrangular, or hexagonal configuration in apellet. However, there is no regularity of arrangement of metal atomsbetween different pellets.

Next, a CAAC-OS analyzed by X-ray diffraction (XRD) is described. Forexample, when the structure of a CAAC-OS including an InGaZnO₄ crystalis analyzed by an out-of-plane method, a peak appears at a diffractionangle (2θ) of around 31° as shown in FIG. 30A. This peak is derived fromthe (009) plane of the InGaZnO₄ crystal, which indicates that crystalsin the CAAC-OS have c-axis alignment, and that the c-axes are aligned ina direction substantially perpendicular to the formation surface or thetop surface of the CAAC-OS.

Note that in structural analysis of the CAAC-OS by an out-of-planemethod, another peak may appear when 2θ is around 36°, in addition tothe peak at 2θ of around 31°. The peak at 2θ of around 36° indicatesthat a crystal having no c-axis alignment is included in part of theCAAC-OS. It is preferable that in the CAAC-OS analyzed by anout-of-plane method, a peak appear when 2θ is around 31° and that a peaknot appear when 2θ is around 36°.

On the other hand, in structural analysis of the CAAC-OS by an in-planemethod in which an X-ray beam is incident on a sample in a directionsubstantially perpendicular to the c-axis, a peak appears when 2θ isaround 56°. This peak is attributed to the (110) plane of the InGaZnO₄crystal. In the case of the CAAC-OS, when analysis (ϕ scan) is performedwith 2θ fixed at around 56° and with the sample rotated using a normalvector of the sample surface as an axis (ϕ axis), as shown in FIG. 30B,a peak is not clearly observed. In contrast, in the case of a singlecrystal oxide semiconductor of InGaZnO₄, when ϕ scan is performed with2θ fixed at around 56°, as shown in FIG. 30C, six peaks which arederived from crystal planes equivalent to the (110) plane are observed.Accordingly, the structural analysis using XRD shows that the directionsof a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction is described. Forexample, when an electron beam with a probe diameter of 300 nm isincident on a CAAC-OS including an InGaZnO₄ crystal in a directionparallel to the sample surface, a diffraction pattern (also referred toas a selected-area transmission electron diffraction pattern) shown inFIG. 31A can be obtained. In this diffraction pattern, spots derivedfrom the (009) plane of an InGaZnO₄ crystal are included. Thus, theelectron diffraction also indicates that pellets included in the CAAC-OShave c-axis alignment and that the c-axes are aligned in a directionsubstantially perpendicular to the formation surface or the top surfaceof the CAAC-OS. Meanwhile, FIG. 31B shows a diffraction pattern obtainedin such a manner that an electron beam with a probe diameter of 300 nmis incident on the same sample in a direction perpendicular to thesample surface. As shown in FIG. 31B, a ring-like diffraction pattern isobserved. Thus, the electron diffraction also indicates that the a-axesand b-axes of the pellets included in the CAAC-OS do not have regularalignment. The first ring in FIG. 31B is considered to be derived fromthe (010) plane, the (100) plane, and the like of the InGaZnO₄ crystal.The second ring in FIG. 31B is considered to be derived from the (110)plane and the like.

As described above, the CAAC-OS is an oxide semiconductor with highcrystallinity. Entry of impurities, formation of defects, or the likemight decrease the crystallinity of an oxide semiconductor. This meansthat the CAAC-OS has small amounts of impurities and defects (e.g.,oxygen vacancies).

Note that the impurity means an element other than the main componentsof the oxide semiconductor, such as hydrogen, carbon, silicon, or atransition metal element. For example, an element (specifically, siliconor the like) having higher strength of bonding to oxygen than a metalelement included in an oxide semiconductor extracts oxygen from theoxide semiconductor, which results in disorder of the atomic arrangementand reduced crystallinity of the oxide semiconductor. A heavy metal suchas iron or nickel, argon, carbon dioxide, or the like has a large atomicradius (or molecular radius), and thus disturbs the atomic arrangementof the oxide semiconductor and decreases crystallinity.

The characteristics of an oxide semiconductor having impurities ordefects might be changed by light, heat, or the like. Impuritiescontained in the oxide semiconductor might serve as carrier traps orcarrier generation sources, for example. Furthermore, oxygen vacanciesin the oxide semiconductor serve as carrier traps or serve as carriergeneration sources when hydrogen is captured therein.

The CAAC-OS having small amounts of impurities and oxygen vacancies isan oxide semiconductor with low carrier density (specifically, lowerthan 8 □ 10¹¹/cm³, preferably lower than 1 □ 10¹¹/cm³, furtherpreferably lower than 1 □ 10¹⁰/cm³, and is higher than or equal to 1 □10⁻⁹/cm³). Such an oxide semiconductor is referred to as a highlypurified intrinsic or substantially highly purified intrinsic oxidesemiconductor. A CAAC-OS has a low impurity concentration and a lowdensity of defect states. Thus, the CAAC-OS can be referred to as anoxide semiconductor having stable characteristics.

<nc-OS>

Next, an nc-OS will be described.

An nc-OS has a region in which a crystal part is observed and a regionin which a crystal part is not clearly observed in a high-resolution TEMimage. In most cases, the size of a crystal part included in the nc-OSis greater than or equal to 1 nm and less than or equal to 10 nm, orgreater than or equal to 1 nm and less than or equal to 3 nm. Note thatan oxide semiconductor including a crystal part whose size is greaterthan 10 nm and less than or equal to 100 nm is sometimes referred to asa microcrystalline oxide semiconductor. In a high-resolution TEM imageof the nc-OS, for example, a grain boundary is not clearly observed insome cases. Note that there is a possibility that the origin of thenanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, acrystal part of the nc-OS may be referred to as a pellet in thefollowing description.

In the nc-OS, a microscopic region (for example, a region with a sizegreater than or equal to 1 nm and less than or equal to 10 nm, inparticular, a region with a size greater than or equal to 1 nm and lessthan or equal to 3 nm) has a periodic atomic arrangement. There is noregularity of crystal orientation between different pellets in thenc-OS. Thus, the orientation of the whole film is not ordered.Accordingly, the nc-OS cannot be distinguished from an a-like OS or anamorphous oxide semiconductor, depending on an analysis method. Forexample, when the nc-OS is analyzed by an out-of-plane method using anX-ray beam having a diameter larger than the size of a pellet, a peakwhich shows a crystal plane does not appear. Furthermore, a diffractionpattern like a halo pattern is observed when the nc-OS is subjected toelectron diffraction using an electron beam with a probe diameter (e.g.,50 nm or larger) that is larger than the size of a pellet. Meanwhile,spots appear in a nanobeam electron diffraction pattern of the nc-OSwhen an electron beam having a probe diameter close to or smaller thanthe size of a pellet is applied. Moreover, in a nanobeam electrondiffraction pattern of the nc-OS, regions with high luminance in acircular (ring) pattern are shown in some cases. Also in a nanobeamelectron diffraction pattern of the nc-OS, a plurality of spots is shownin a ring-like region in some cases.

Since there is no regularity of crystal orientation between the pellets(nanocrystals) as mentioned above, the nc-OS can also be referred to asan oxide semiconductor including random aligned nanocrystals (RANC) oran oxide semiconductor including non-aligned nanocrystals (NANC).

The nc-OS is an oxide semiconductor that has high regularity as comparedwith an amorphous oxide semiconductor. Therefore, the nc-OS is likely tohave a lower density of defect states than an a-like OS and an amorphousoxide semiconductor. Note that there is no regularity of crystalorientation between different pellets in the nc-OS. Therefore, the nc-OShas a higher density of defect states than the CAAC-OS.

<a-Like OS>

An a-like OS has a structure between those of the nc-OS and theamorphous oxide semiconductor.

In a high-resolution TEM image of the a-like OS, a void may be observed.Furthermore, in the high-resolution TEM image, there are a region wherea crystal part is clearly observed and a region where a crystal part isnot observed.

The a-like OS has an unstable structure because it contains a void. Toverify that an a-like OS has an unstable structure as compared with aCAAC-OS and an nc-OS, a change in structure caused by electronirradiation is described below.

An a-like OS (referred to as Sample A), an nc-OS (referred to as SampleB), and a CAAC-OS (referred to as Sample C) are prepared as samplessubjected to electron irradiation. Each of the samples is an In-Ga—Znoxide.

First, a high-resolution cross-sectional TEM image of each sample isobtained. The high-resolution cross-sectional TEM images show that allthe samples have crystal parts.

Note that which part is regarded as a crystal part is determined asfollows. It is known that a unit cell of an InGaZnO₄ crystal has astructure in which nine layers including three In—O layers and sixGa—Zn—O layers are stacked in the c-axis direction. The distance betweenthe adjacent layers is equivalent to the lattice spacing on the (009)plane (also referred to as d value). The value is calculated to be 0.29nm from crystal structural analysis. Accordingly, a portion where thelattice spacing between lattice fringes is greater than or equal to 0.28nm and less than or equal to 0.30 nm is regarded as a crystal part ofInGaZnO₄. Each of lattice fringes corresponds to the a-b plane of theInGaZnO₄ crystal.

FIG. 32 shows change in the average size of crystal parts (at 22 pointsto 45 points) in each sample. Note that the crystal part sizecorresponds to the length of a lattice fringe. FIG. 32 indicates thatthe crystal part size in the a-like OS increases with an increase in thecumulative electron dose. Specifically, as shown by (1) in FIG. 32, acrystal part of approximately 1.2 nm (also referred to as an initialnucleus) at the start of TEM observation grows to a size ofapproximately 2.6 nm at a cumulative electron dose of 4.2×10⁸ e⁻/nm². Incontrast, the crystal part size in the nc-OS and the CAAC-OS showslittle change from the start of electron irradiation to a cumulativeelectron dose of 4.2×10⁸ e⁻/nm². Specifically, as shown by (2) and (3)in FIG. 32, the average crystal sizes in an nc-OS and a CAAC-OS areapproximately 1.4 nm and approximately 2.1 nm, respectively, regardlessof the cumulative electron dose.

In this manner, growth of the crystal part in the a-like OS is inducedby electron irradiation. In contrast, in the nc-OS and the CAAC-OS,growth of the crystal part is hardly induced by electron irradiation.Therefore, the a-like OS has an unstable structure as compared with thenc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS becauseit contains a void. Specifically, the density of the a-like OS is higherthan or equal to 78.6% and lower than 92.3% of the density of the singlecrystal oxide semiconductor having the same composition. The density ofeach of the nc-OS and the CAAC-OS is higher than or equal to 92.3% andlower than 100% of the density of the single crystal oxide semiconductorhaving the same composition. Note that it is difficult to deposit anoxide semiconductor having a density of lower than 78% of the density ofthe single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor having an atomicratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO₄ with arhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the caseof the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, thedensity of the a-like OS is higher than or equal to 5.0 g/cm³ and lowerthan 5.9 g/cm³. For example, in the case of the oxide semiconductorhaving an atomic ratio of In:Ga:Zn=1:1:1, the density of each of thenc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm³ and lowerthan 6.3 g/cm³.

Note that there is a possibility that an oxide semiconductor having acertain composition cannot exist in a single crystal structure. In thatcase, single crystal oxide semiconductors with different compositionsare combined at an adequate ratio, which makes it possible to calculatedensity equivalent to that of a single crystal oxide semiconductor withthe desired composition. The density of a single crystal oxidesemiconductor having the desired composition can be calculated using aweighted average according to the combination ratio of the singlecrystal oxide semiconductors with different compositions. Note that itis preferable to use as few kinds of single crystal oxide semiconductorsas possible to calculate the density.

As described above, oxide semiconductors have various structures andvarious properties. Note that an oxide semiconductor may be a stackedlayer including two or more of an amorphous oxide semiconductor, ana-like OS, an nc-OS, and a CAAC-OS, for example.

Embodiment 12

In this embodiment, an example of a circuit of a semiconductor deviceincluding a transistor or the like of one embodiment of the presentinvention will be described.

<CMOS Inverter>

A circuit diagram in FIG. 33A shows a configuration of what is called aCMOS inverter in which a p-channel transistor 2200 and an n-channeltransistor 2100 are connected to each other in series and in which gatesof them are connected to each other.

<Structure 1 of Semiconductor Device>

FIG. 34 is a cross-sectional view of the semiconductor device of FIG.33A. The semiconductor device shown in FIG. 34 includes the transistor2200 and the transistor 2100. The transistor 2100 is placed above thetransistor 2200. Any of the transistors described in the aboveembodiments can be used as the transistor 2100. Thus, the descriptionregarding the above-mentioned transistors can be referred to for thetransistor 2100 as appropriate.

The transistor 2200 shown in FIG. 34 is a transistor using asemiconductor substrate 450. The transistor 2200 includes a region 472 ain the semiconductor substrate 450, a region 472 b in the semiconductorsubstrate 450, an insulator 462, and a conductor 454.

In the transistor 2200, the regions 472 a and 472 b have functions of asource region and a drain region. The insulator 462 serves as a gateinsulator. The conductor 454 serves as a gate electrode. Thus, theresistance of a channel formation region can be controlled by apotential applied to the conductor 454. In other words, conduction ornon-conduction between the region 472 a and the region 472 b can becontrolled by the potential applied to the conductor 454.

For the semiconductor substrate 450, a single-material semiconductorsubstrate formed using silicon, germanium, or the like or asemiconductor substrate formed using silicon carbide, silicon germanium,gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or thelike may be used, for example. A single crystal silicon substrate ispreferably used as the semiconductor substrate 450.

For the semiconductor substrate 450, a semiconductor substrate includingimpurities imparting n-type conductivity is used. However, asemiconductor substrate including impurities imparting p-typeconductivity may be used as the semiconductor substrate 450. In thatcase, a well including impurities imparting the n-type conductivity maybe provided in a region where the transistor 2200 is formed.Alternatively, the semiconductor substrate 450 may be an i-typesemiconductor substrate.

The top surface of the semiconductor substrate 450 preferably has a(110) plane. Thus, on-state characteristics of the transistor 2200 canbe improved.

The regions 472 a and 472 b are regions including impurities impartingthe p-type conductivity. Accordingly, the transistor 2200 has astructure of a p-channel transistor.

Note that the transistor 2200 is apart from an adjacent transistor by aregion 460 and the like. The region 460 is an insulating region.

The semiconductor device illustrated in FIG. 34 includes an insulator464, an insulator 466, an insulator 468, a conductor 480 a, a conductor480 b, a conductor 480 c, a conductor 478 a, a conductor 478 b, aconductor 478 c, a conductor 476 a, a conductor 476 b, a conductor 474a, a conductor 474 b, a conductor 474 c, a conductor 496 a, a conductor496 b, a conductor 496 c, a conductor 496 d, a conductor 498 a, aconductor 498 b, a conductor 498 c, an insulator 489, an insulator 490,an insulator 492, an insulator 493, an insulator 494, and an insulator495.

The insulator 464 is placed over the transistor 2200. The insulator 466is placed over the insulator 464. The insulator 468 is placed over theinsulator 466. The insulator 489 is placed over the insulator 468. Thetransistor 2100 is placed over the insulator 489. The insulator 493 isplaced over the transistor 2100. The insulator 494 is placed over theinsulator 493.

The insulator 464 includes an opening reaching the region 472 a, anopening reaching the region 472 b, and an opening reaching the conductor454. In the openings, the conductor 480 a, the conductor 480 b, and theconductor 480 c are embedded.

The insulator 466 includes an opening reaching the conductor 480 a, anopening reaching the conductor 480 b, and an opening reaching theconductor 480 c. In the openings, the conductor 478 a, the conductor 478b, and the conductor 478 c are embedded.

The insulator 468 includes an opening reaching the conductor 478 b andan opening reaching the conductor 478 c. In the openings, the conductor476 a and the conductor 476 b are embedded.

The insulator 489 includes an opening overlapping with a channelformation region of the transistor 2100, an opening reaching theconductor 476 a, and an opening reaching the conductor 476 b. In theopenings, the conductor 474 a, the conductor 474 b, and the conductor474 c are embedded.

The conductor 474 a may serve as a gate electrode of the transistor2100. The electrical characteristics of the transistor 2100, such as thethreshold voltage, may be controlled by application of a predeterminedpotential to the conductor 474 a, for example. The conductor 474 a maybe electrically connected to the conductor 504 having a function of thegate electrode of the transistor 2100, for example. In that case,on-state current of the transistor 2100 can be increased. Furthermore, apunch-through phenomenon can be suppressed; thus, the electricalcharacteristics of the transistor 2100 in a saturation region can bestable. Note that the conductor 474 a corresponds to the conductor 413in the above embodiment and thus, the description of the conductor 413can be referred to for details about the conductor 474 a.

The insulator 490 includes an opening reaching the conductor 474 b. Notethat the insulator 490 corresponds to the insulator 402 in the aboveembodiment and thus, the description of the insulator 402 can bereferred to for details about the insulator 490.

The insulator 495 includes the opening reaching the conductor 474 bthrough a conductor 507 b that is one of a source and a drain of thetransistor 2100, an opening reaching a conductor 507 a that is the otherof the source and the drain of the transistor 2100, an opening reachingthe conductor 504 that is the gate electrode of the transistor 2100, andthe opening reaching the conductor 474 c. Note that the insulator 495corresponds to the insulator 410 in the above embodiment and thus, thedescription of the insulator 410 can be referred to for details aboutthe insulator 495.

The insulator 493 includes the opening reaching the conductor 474 bthrough the conductor 507 b that is one of the source and the drain ofthe transistor 2100, the opening reaching the conductor 507 a that isthe other of the source and the drain of the transistor 2100, theopening reaching the conductor 504 that is the gate electrode of thetransistor 2100, and the opening reaching the conductor 474 c. In theopenings, the conductor 496 a, the conductor 496 b, the conductor 496 c,and the conductor 496 d are embedded. Note that in some cases, anopening provided in a component of the transistor 2100 or the like maybe positioned between openings provided in other components.

The insulator 494 includes an opening reaching the conductor 496 a, anopening reaching the conductor 496 b and the conductor 496 d, and anopening reaching the conductor 496 c. In the openings, the conductor 498a, the conductor 498 b, and the conductor 498 c are embedded.

The insulators 464, 466, 468, 489, 493, and 494 may each be formed tohave, for example, a single-layer structure or a stacked-layer structureincluding an insulator containing boron, carbon, nitrogen, oxygen,fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon,gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium,or tantalum.

The insulator that has a function of blocking oxygen and impurities suchas hydrogen is preferably included in at least one of the insulators464, 466, 468, 489, 493, and 494. When an insulator that has a functionof blocking oxygen and impurities such as hydrogen is placed near thetransistor 2100, the electrical characteristics of the transistor 2100can be stable.

An insulator with a function of blocking oxygen and impurities such ashydrogen may be formed to have a single-layer structure or astacked-layer structure including an insulator containing, for example,boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum.

Each of the conductor 480 a, the conductor 480 b, the conductor 480 c,the conductor 478 a, the conductor 478 b, the conductor 478 c, theconductor 476 a, the conductor 476 b, the conductor 474 a, the conductor474 b, the conductor 474 c, the conductor 496 a, the conductor 496 b,the conductor 496 c, the conductor 496 d, the conductor 498 a, theconductor 498 b, and the conductor 498 c may be formed to have, forexample, a single-layer structure or a stacked-layer structure includinga conductor containing one or more kinds selected from boron, nitrogen,oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium,manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium,molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. Analloy or a compound containing the above element may be used, forexample, and a conductor containing aluminum, a conductor containingcopper and titanium, a conductor containing copper and manganese, aconductor containing indium, tin, and oxygen, a conductor containingtitanium and nitrogen, or the like may be used.

Note that a semiconductor device in FIG. 35 is the same as thesemiconductor device in FIG. 34 except for the structure of thetransistor 2200. Therefore, the description of the semiconductor devicein FIG. 34 is referred to for the semiconductor device in FIG. 35. Inthe semiconductor device in FIG. 35, the transistor 2200 is a Fin-typetransistor. The effective channel width is increased in the Fin-typetransistor 2200, whereby the on-state characteristics of the transistor2200 can be improved. In addition, since contribution of the electricfield of the gate electrode can be increased, the off-statecharacteristics of the transistor 2200 can be improved.

Note that a semiconductor device in FIG. 36 is the same as thesemiconductor device in FIG. 34 except for the structure of thetransistor 2200. Therefore, the description of the semiconductor devicein FIG. 34 is referred to for the semiconductor device in FIG. 36.Specifically, in the semiconductor device in FIG. 36, the transistor2200 is formed in the semiconductor substrate 450 that is an SOIsubstrate. In the structure in FIG. 36, a region 456 is apart from thesemiconductor substrate 450 with an insulator 452 provided therebetween.Since the SOI substrate is used as the semiconductor substrate 450, apunch-through phenomenon and the like can be suppressed; thus, theoff-state characteristics of the transistor 2200 can be improved. Notethat the insulator 452 can be formed by turning the semiconductorsubstrate 450 into an insulator. For example, silicon oxide can be usedas the insulator 452.

In each of the semiconductor devices shown in FIG. 34, FIG. 35, and FIG.36, a p-channel transistor is formed utilizing a semiconductorsubstrate, and an n-channel transistor is formed above that; therefore,an occupation area of the element can be reduced. That is, theintegration degree of the semiconductor device can be improved. Inaddition, the manufacturing process can be simplified compared to thecase where an n-channel transistor and a p-channel transistor are formedutilizing the same semiconductor substrate; therefore, the productivityof the semiconductor device can be increased. Moreover, the yield of thesemiconductor device can be improved. For the p-channel transistor, somecomplicated steps such as formation of lightly doped drain (LDD)regions, formation of a shallow trench structure, or distortion designcan be omitted in some cases. Therefore, the productivity and yield ofthe semiconductor device can be increased in some cases, compared to asemiconductor device where an n-channel transistor is formed utilizingthe semiconductor substrate.

<CMOS Analog Switch>

A circuit diagram in FIG. 33B shows a configuration in which sources ofthe transistors 2100 and 2200 are connected to each other and drains ofthe transistors 2100 and 2200 are connected to each other. With such aconfiguration, the transistors can function as what is called a CMOSanalog switch.

<Memory Device 1>

An example of a semiconductor device (memory device) which includes thetransistor of one embodiment of the present invention, which can retainstored data even when not powered, and which has an unlimited number ofwrite cycles is shown in FIGS. 37A and 37B.

The semiconductor device illustrated in FIG. 37A includes a transistor3200 using a first semiconductor, a transistor 3300 using a secondsemiconductor, and a capacitor 3400. Note that a transistor similar tothe transistor 2100 can be used as the transistor 3300.

Note that the transistor 3300 is preferably a transistor with a lowoff-state current. For example, a transistor using an oxidesemiconductor can be used as the transistor 3300. Since the off-statecurrent of the transistor 3300 is low, stored data can be retained for along period at a predetermined node of the semiconductor device. Inother words, power consumption of the semiconductor device can bereduced because refresh operation becomes unnecessary or the frequencyof refresh operation can be extremely low.

In FIG. 37A, a first wiring 3001 is electrically connected to a sourceof the transistor 3200. A second wiring 3002 is electrically connectedto a drain of the transistor 3200. A third wiring 3003 is electricallyconnected to one of a source and a drain of the transistor 3300. Afourth wiring 3004 is electrically connected to a gate of the transistor3300. A gate of the transistor 3200 and the other of the source and thedrain of the transistor 3300 are electrically connected to one electrodeof the capacitor 3400. A fifth wiring 3005 is electrically connected tothe other electrode of the capacitor 3400.

The semiconductor device in FIG. 37A has a feature that the potential ofthe gate of the transistor 3200 can be retained, and thus enableswriting, retaining, and reading of data as follows.

Writing and retaining of data are described. First, the potential of thefourth wiring 3004 is set to a potential at which the transistor 3300 ison, so that the transistor 3300 is turned on. Accordingly, the potentialof the third wiring 3003 is supplied to a node FG where the gate of thetransistor 3200 and the one electrode of the capacitor 3400 areelectrically connected to each other. That is, a predetermined electriccharge is supplied to the gate of the transistor 3200 (writing). Here,one of two kinds of electric charges providing different potentiallevels (hereinafter referred to as a low-level electric charge and ahigh-level electric charge) is supplied. After that, the potential ofthe fourth wiring 3004 is set to a potential at which the transistor3300 is off, so that the transistor 3300 is turned off. Thus, theelectric charge is held at the node FG (retaining).

Since the off-state current of the transistor 3300 is low, the electriccharge of the node FG is retained for a long time.

Next, reading of data is described. An appropriate potential (a readingpotential) is supplied to the fifth wiring 3005 while a predeterminedpotential (a constant potential) is supplied to the first wiring 3001,whereby the potential of the second wiring 3002 varies depending on theamount of electric charge retained in the node FG. This is because inthe case of using an re-channel transistor as the transistor 3200, anapparent threshold voltage V_(th_H) at the time when the high-levelelectric charge is given to the gate of the transistor 3200 is lowerthan an apparent threshold voltage V_(th_L) at the time when thelow-level electric charge is given to the gate of the transistor 3200.Here, an apparent threshold voltage refers to the potential of the fifthwiring 3005 which is needed to make the transistor 3200 be in “onstate”. Thus, the potential of the fifth wiring 3005 is set to apotential V₀ which is between V_(th_H) and V_(th_L), whereby electriccharge supplied to the node FG can be determined. For example, in thecase where the high-level electric charge is supplied to the node FG inwriting and the potential of the fifth wiring 3005 is V₀ (>V_(th_H)),the transistor 3200 is brought into “on state”. In the case where thelow-level electric charge is supplied to the node FG in writing, evenwhen the potential of the fifth wiring 3005 is V₀ (<V_(th_L)), thetransistor 3200 still remains in “off state”. Thus, the data retained inthe node FG can be read by determining the potential of the secondwiring 3002.

Note that in the case where memory cells are arrayed, it is necessarythat data of a desired memory cell be read in read operation. Forexample, a configuration in which only data of a desired memory cell canbe read by supplying a potential at which the transistor 3200 is broughtinto an “off state” regardless of the charge supplied to the node FG,that is, a potential lower than V_(th_H) to the fifth wiring 3005 ofmemory cells from which data is not read may be employed. Alternatively,a configuration in which only data of a desired memory cell can be readby supplying a potential at which the transistor 3200 is brought into an“on state” regardless of the charge supplied to the node FG, that is, apotential higher than V_(th_L) to the fifth wiring 3005 of memory cellsfrom which data is not read may be employed.

Although an example in which two kinds of electric charges are retainedin the node FG, the semiconductor device of the present invention is notlimited to this example. For example, a structure in which three or morekinds of electric charges can be retained in the node FG of thesemiconductor device may be employed. With such a structure, thesemiconductor device can be multi-valued and the storage capacity can beincreased.

<Structure of Memory Device 1>

FIG. 38 is a cross-sectional view of the semiconductor device of FIG.37A. The semiconductor device shown in FIG. 38 includes the transistor3200, the transistor 3300, and the capacitor 3400. The transistor 3300and the capacitor 3400 are placed above the transistor 3200. Note thatfor the transistor 3300, the description of the above transistor 2100 isreferred to. Furthermore, for the transistor 3200, the description ofthe transistor 2200 in FIG. 34 is referred to. Note that although thetransistor 2200 is illustrated as a p-channel transistor in FIG. 34, thetransistor 3200 may be an n-channel transistor.

The transistor 2200 illustrated in FIG. 38 is a transistor using thesemiconductor substrate 450. The transistor 2200 includes the region 472a in the semiconductor substrate 450, the region 472 b in thesemiconductor substrate 450, the insulator 462, and the conductor 454.

The semiconductor device illustrated in FIG. 38 includes the insulator464, the insulator 466, the insulator 468, the conductor 480 a, theconductor 480 b, the conductor 480 c, the conductor 478 a, the conductor478 b, the conductor 478 c, the conductor 476 a, the conductor 476 b,the conductor 474 a, the conductor 474 b, the conductor 474 c, theconductor 496 a, the conductor 496 b, the conductor 496 c, the conductor496 d, the conductor 498 a, the conductor 498 b, the conductor 498 c,the insulator 489, the insulator 490, the insulator 492, the insulator493, the insulator 494, and the insulator 495.

The insulator 464 is provided over the transistor 3200. The insulator466 is provided over the insulator 464. The insulator 468 is providedover the insulator 466. The insulator 489 is provided over the insulator468. The transistor 2100 is provided over the insulator 489. Theinsulator 493 is provided over the transistor 2100. The insulator 494 isprovided over the insulator 493.

The insulator 464 has an opening reaching the region 472 a, an openingreaching the region 472 b, and an opening reaching the conductor 454. Inthe openings, the conductor 480 a, the conductor 480 b, and theconductor 480 c are embedded.

The insulator 466 includes an opening reaching the conductor 480 a, anopening reaching the conductor 480 b, and an opening reaching theconductor 480 c. In the openings, the conductor 478 a, the conductor 478b, and the conductor 478 c are embedded.

The insulator 468 includes an opening reaching the conductor 478 b andan opening reaching the conductor 478 c. In the openings, the conductor476 a and the conductor 476 b are embedded.

The insulator 489 includes an opening overlapping with a channelformation region of the transistor 3300, an opening reaching theconductor 476 a, and an opening reaching the conductor 476 b. In theopenings, the conductor 474 a, the conductor 474 b, and the conductor474 c are embedded.

The conductor 474 a may serve as a bottom gate electrode of thetransistor 3300. Alternatively, for example, electrical characteristicssuch as the threshold voltage of the transistor 3300 may be controlledby application of a constant potential to the conductor 474 a. Furtheralternatively, for example, the conductor 474 a and the conductor 504that is a top gate electrode of the transistor 3300 may be electricallyconnected to each other. Thus, the on-state current of the transistor3300 can be increased. A punch-through phenomenon can be suppressed;thus, stable electrical characteristics in a saturation region of thetransistor 3300 can be obtained.

The insulator 490 includes an opening reaching the conductor 474 b andan opening reaching the conductor 474 c. Note that the insulator 490corresponds to the insulator 402 in the above embodiment and thus, thedescription of the insulator 402 can be referred to for details aboutthe insulator 490.

The insulator 495 includes an opening reaching the conductor 474 bthrough the conductor 507 b that is one of a source and a drain of thetransistor 3300, an opening reaching the conductor 515 through theconductor 507 a that is the other of the source and the drain of thetransistor 3300, and an opening reaching the conductor 474 c through theconductor 507 a that is the other of the source and the drain of thetransistor 3300. Note that the insulator 495 corresponds to theinsulator 410 in the above embodiment and thus, the description of theinsulator 410 can be referred to for details about the insulator 495.

The insulator 493 includes an opening reaching the conductor 514 thatoverlaps with the conductor 515 with the insulator 511 positionedtherebetween, an opening reaching the conductor that is the gateelectrode of the transistor 3300, and the opening reaching the conductor516 that is electrically connected to the conductor 507 b that is theone of the source and the drain of the transistor 3300. In the openings,the conductor 496 e, the conductor 496 b, and the conductor 496 f areembedded. Note that in some cases, an opening provided in a component ofthe transistor 3300 or the like is through other components.

The insulator 494 includes an opening reaching the conductor 496 e, anopening reaching the conductor 496 b, and an opening reaching theconductor 496 f. In the openings, the conductors 498 a, 498 b, and 498 care embedded.

At least one of the insulators 464, 466, 468, 489, 493, and 494preferably has a function of blocking oxygen and impurities such ashydrogen. When an insulator that has a function of blocking oxygen andimpurities such as hydrogen is placed near the transistor 3300, theelectrical characteristics of the transistor 3300 can be stable.

The source or drain of the transistor 3200 is electrically connected tothe conductor 507 b that is one of the source and the drain of thetransistor 3300 through the conductor 480 b, the conductor 478 b, theconductor 476 a, the conductor 474 b, and the conductor 496 c. Theconductor 454 that is the gate electrode of the transistor 3200 iselectrically connected to the conductor 507 a that is the other of thesource and the drain of the transistor 3300 through the conductor 480 c,the conductor 478 c, the conductor 476 b, the conductor 474 c, and theconductor 496 d.

The capacitor 3400 includes a conductor 515, the conductor 514, and theinsulator 511.

For the structures of other components, the description of FIG. 34 andthe like can be referred to as appropriate.

A semiconductor device in FIG. 39 is the same as the semiconductordevice in FIG. 38 except for the structure of the transistor 3200.Therefore, the description of the semiconductor device in FIG. 38 isreferred to for the semiconductor device in FIG. 39. Specifically, inthe semiconductor device in FIG. 39, the transistor 3200 is a Fin-typetransistor. For the Fin-type transistor 3200, the description of thetransistor 2200 in FIG. 35 is referred to. Note that although thetransistor 2200 is illustrated as a p-channel transistor in FIG. 35, thetransistor 3200 may be an n-channel transistor.

A semiconductor device in FIG. 40 is the same as the semiconductordevice in FIG. 38 except for the structure of the transistor 3200.Therefore, the description of the semiconductor device in FIG. 38 isreferred to for the semiconductor device in FIG. 40. Specifically, inthe semiconductor device in FIG. 40, the transistor 3200 is provided inthe semiconductor substrate 450 that is an SOI substrate. For thetransistor 3200, which is provided in the semiconductor substrate 450(SOI substrate), the description of the transistor 2200 in FIG. 36 isreferred to. Note that although the transistor 2200 is illustrated as ap-channel transistor in FIG. 36, the transistor 3200 may be an n-channeltransistor.

<Memory Device 2>

The semiconductor device in FIG. 37B is different from the semiconductordevice in FIG. 37A in that the transistor 3200 is not provided. Also inthis case, data can be written and retained in a manner similar to thatof the semiconductor device in FIG. 37A.

Reading of data in the semiconductor device in FIG. 37B is described.When the transistor 3300 is brought into an on state, the third wiring3003 which is in a floating state and the capacitor 3400 are broughtinto conduction, and the electric charge is redistributed between thethird wiring 3003 and the capacitor 3400. As a result, the potential ofthe third wiring 3003 is changed. The amount of change in the potentialof the third wiring 3003 varies depending on the potential of the oneelectrode of the capacitor 3400 (or the electric charge accumulated inthe capacitor 3400).

For example, the potential of the third wiring 3003 after the chargeredistribution is (C_(B)×V_(B0)+C×V)/(C_(B)+C), where V is the potentialof the one electrode of the capacitor 3400, C is the capacitance of thecapacitor 3400, C_(B) is the capacitance component of the third wiring3003, and V_(B0) is the potential of the third wiring 3003 before thecharge redistribution. Thus, it can be found that, assuming that thememory cell is in either of two states in which the potential of the oneelectrode of the capacitor 3400 is V₁ and V₀ (V₁>V₀), the potential ofthe third wiring 3003 in the case of retaining the potential V₁(=(C_(B)×V_(B0)+C×V₁)/(C_(B)+C)) is higher than the potential of thethird wiring 3003 in the case of retaining the potential V₀(=(C_(B)×V_(B0)+C×V₀)/(C_(B)+C)).

Then, by comparing the potential of the third wiring 3003 with apredetermined potential, data can be read.

In this case, a transistor including the first semiconductor may be usedfor a driver circuit for driving a memory cell, and a transistorincluding the second semiconductor may be stacked over the drivercircuit as the transistor 3300.

When including a transistor using an oxide semiconductor and having alow off-state current, the semiconductor device described above canretain stored data for a long time. In other words, power consumption ofthe semiconductor device can be reduced because refresh operationbecomes unnecessary or the frequency of refresh operation can beextremely low. Moreover, stored data can be retained for a long timeeven when power is not supplied (note that a potential is preferablyfixed).

In the semiconductor device, high voltage is not needed for writing dataand deterioration of elements is less likely to occur. Unlike in aconventional nonvolatile memory, for example, it is not necessary toinject and extract electrons into and from a floating gate; thus, aproblem such as deterioration of an insulator is not caused. That is,the semiconductor device of one embodiment of the present invention doesnot have a limit on the number of times data can be rewritten, which isa problem of a conventional nonvolatile memory, and the reliabilitythereof is drastically improved. Furthermore, data is written dependingon the on/off state of the transistor, whereby high-speed operation canbe achieved.

<Memory Device 3>

A modification example of the semiconductor device (memory device)illustrated in FIG. 37A will be described with reference to a circuitdiagram in FIG. 41.

The semiconductor device illustrated in FIG. 41 includes a transistor4100, a transistor 4200, a transistor 4300, a transistor 4400, acapacitor 4500, and a capacitor 4600. Here, a transistor similar to thetransistor 3200 can be used as the transistor 4100, and transistorssimilar to the transistor 3300 can be used as the transistors 4200,4300, and 4400. Although not illustrated in FIG. 41, a plurality ofsemiconductor devices in FIG. 41 are provided in a matrix. Thesemiconductor devices in FIG. 41 can control writing and reading of adata voltage in accordance with a signal or a potential supplied to awiring 4001, a wiring 4003, a wiring 4005, a wiring 4006, a wiring 4007,a wiring 4008, and a wiring 4009.

One of a source and a drain of the transistor 4100 is connected to thewiring 4003. The other of the source and the drain of the transistor4100 is connected to the wiring 4001. Although the transistor 4100 is ap-channel transistor in FIG. 41, the transistor 4100 may be an n-channeltransistor.

The semiconductor device in FIG. 41 includes two data retentionportions. For example, a first data retention portion retains anelectric charge between one of a source and a drain of the transistor4400, one electrode of the capacitor 4600, and one of a source and adrain of the transistor 4200 which are connected to a node FG1. A seconddata retention portion retains an electric charge between a gate of thetransistor 4100, the other of the source and the drain of the transistor4200, one of a source and a drain of the transistor 4300, and oneelectrode of the capacitor 4500 which are connected to a node FG2.

The other of the source and the drain of the transistor 4300 isconnected to the wiring 4003. The other of the source and the drain ofthe transistor 4400 is connected to the wiring 4001. A gate of thetransistor 4400 is connected to the wiring 4005. A gate of thetransistor 4200 is connected to the wiring 4006. A gate of thetransistor 4300 is connected to the wiring 4007. The other electrode ofthe capacitor 4600 is connected to the wiring 4008. The other electrodeof the capacitor 4500 is connected to the wiring 4009.

The transistors 4200, 4300, and 4400 each function as a switch forcontrol of writing a data voltage and retaining an electric charge. Notethat, as each of the transistors 4200, 4300, and 4400, it is preferableto use a transistor having a low current that flows between a source anda drain in an off state (low off-state current). As an example of thetransistor with a low off-state current, a transistor including an oxidesemiconductor in its channel formation region (an OS transistor) ispreferably used. An OS transistor has a low off-state current and can bemanufactured to overlap with a transistor including silicon, forexample. Although the transistors 4200, 4300, and 4400 are n-channeltransistors in FIG. 41, the transistors 4200, 4300, and 4400 may bep-channel transistors.

The transistors 4200 and 4300 and the transistor 4400 are preferablyprovided in different layers even when the transistors 4200, 4300, and4400 are transistors including oxide semiconductors. In other words, thesemiconductor device in FIG. 41 preferably includes, as illustrated inFIG. 41, a first layer 4021 where the transistor 4100 is provided, asecond layer 4022 where the transistors 4200 and 4300 are provided, anda third layer 4023 where the transistor 4400 is provided. By stackinglayers where transistors are provided, the circuit area can be reduced,so that the size of the semiconductor device can be reduced.

Next, operation of writing data to the semiconductor device illustratedin FIG. 41 is described.

First, operation of writing data voltage to the data retention portionconnected to the node FG1 (hereinafter referred to as writingoperation 1) is described. In the following description, data voltagewritten to the data retention portion connected to the node FG1 isV_(D1), and the threshold voltage of the transistor 4100 is V_(th).

In the writing operation 1, the potential of the wiring 4003 is set atV_(D1), and after the potential of the wiring 4001 is set at a groundpotential, the wiring 4001 is brought into an electrically floatingstate. The wirings 4005 and 4006 are set at a high level. The wirings4007 to 4009 are set at a low level. Then, the potential of the node FG2in the electrically floating state is increased, so that a current flowsthrough the transistor 4100. The current flows through the transistor4100, so that the potential of the wiring 4001 is increased. Thetransistors 4400 and 4200 are turned on. Thus, as the potential of thewiring 4001 is increased, the potentials of the nodes FG1 and FG2 areincreased. When the potential of the node FG2 is increased and a voltage(V_(gs)) between the gate and the source of the transistor 4100 becomesthe threshold voltage V_(th) of the transistor 4100, the current flowingthrough the transistor 4100 is decreased. Accordingly, the potentials ofthe wiring 4001 and the nodes FG1 and FG2 stop increasing, so that thepotentials of the nodes FG1 and FG2 are fixed at “V_(D1)−V_(th)” inwhich V_(D1) is decreased by V_(th).

When a current flows through the transistor 4100, V_(D1) supplied to thewiring 4003 is supplied to the wiring 4001, so that the potentials ofthe nodes FG1 and FG2 are increased. When the potential of the node FG2becomes “V_(D1)−V_(th)” with the increase in the potentials, V_(gs) ofthe transistor 4100 becomes V_(th), so that the current flow is stopped.

Next, operation of writing data voltage to the data retention portionconnected to the node FG2 (hereinafter referred to as writing operation2) is described. In the following description, data voltage written tothe data retention portion connected to the node FG2 is V_(D2).

In the writing operation 2, the potential of the wiring 4001 is set atV_(D2), and after the potential of the wiring 4003 is set at a groundpotential, the wiring 4003 is brought into an electrically floatingstate. The wiring 4007 is set at the high level. The wirings 4005, 4006,4008, and 4009 are set at the low level. The transistor 4300 is turnedon, so that the wiring 4003 is set at the low level. Thus, the potentialof the node FG2 is decreased to the low level, so that the current flowsthrough the transistor 4100. By the current flow, the potential of thewiring 4003 is increased. The transistor 4300 is turned on. Thus, as thepotential of the wiring 4003 is increased, the potential of the node FG2is increased. When the potential of the node FG2 is increased and V_(gs)of the transistor 4100 becomes V_(th) of the transistor 4100, thecurrent flowing through the transistor 4100 is decreased. Accordingly,an increase in the potentials of the wiring 4003 and the node FG2 isstopped, so that the potential of the node FG2 is fixed at“V_(D2)−V_(th)” in which V_(D2) is decreased by V_(th).

In other words, when a current flows through the transistor 4100, V_(D2)supplied to the wiring 4001 is supplied to the wiring 4003, so that thepotential of the node FG2 is increased. When the potential of the nodeFG2 becomes “V_(D2)−V_(th)” with the increase in the potential, V_(gs)of the transistor 4100 becomes V_(th), so that the current flow isstopped. At this time, the transistors 4200 and 4400 are off and thepotential of the node FG1 remains at “V_(D1)−V_(th)” written in thewriting operation 1.

In the semiconductor device in FIG. 41, after data voltages are writtento the plurality of data retention portions, the wiring 4009 is set atthe high level, so that the potentials of the nodes FG1 and FG2 areincreased. Then, the transistors are turned off to stop movement ofelectric charges; thus, the written data voltages are retained.

By the above-described writing operation of the data voltage to thenodes FG1 and FG2, the data voltages can be retained in the plurality ofdata retention portions. Although examples where “V_(D1)−V_(th)” and“V_(D2)−V_(th)” are used as the written potentials are described, theyare data voltages corresponding to multilevel data. Therefore, in thecase where the data retention portions each retain 4-bit data, 16-value“V_(D1)−V_(th)” and 16-value “V_(D2)−V_(th)” can be obtained.

Next, operation of reading data from the semiconductor deviceillustrated in FIG. 41 is described.

First, operation of reading data voltage to the data retention portionconnected to the node FG2 (hereinafter referred to as readingoperation 1) is described.

In the reading operation 1, after precharge is performed, the wiring4003 in an electrically floating state is discharged. The wirings 4005to 4008 are set low. When the wiring 4009 is set low, the potential ofthe node FG2 which is electrically floating is set at “V_(D2)−V_(th)”.The potential of the node FG2 is decreased, so that a current flowsthrough the transistor 4100. By the current flow, the potential of thewiring 4003 which is electrically floating is decreased. As thepotential of the wiring 4003 is decreased, V_(gs) of the transistor 4100is decreased. When V_(gs) of the transistor 4100 becomes V_(th) of thetransistor 4100, the current flowing through the transistor 4100 isdecreased. In other words, the potential of the wiring 4003 becomes“V_(D2)” which is larger than the potential of the node FG2,“V_(D2)−V_(th)”, by V_(th). The potential of the wiring 4003 correspondsto the data voltage of the data retention portion connected to the nodeFG2. The data voltage of the read analog value is subjected to A/Dconversion, so that data of the data retention portion connected to thenode FG2 is obtained.

In other words, the wiring 4003 after precharge is brought into afloating state and the potential of the wiring 4009 is changed from highto low, whereby a current flows through the transistor 4100. When thecurrent flows, the potential of the wiring 4003 which is in a floatingstate is decreased to be “V_(D2)”. In the transistor 4100, V_(gs)between “V_(D2)−V_(th)” of the node FG2 and “V_(D2)” of the wiring 4003becomes V_(th), so that the current stops. Then, “V_(D2)” written in thewriting operation 2 is read to the wiring 4003.

After data in the data retention portion connected to the node FG2 isobtained, the transistor 4300 is turned on to discharge “V_(D2)−V_(th)”of the node FG2.

Then, the electric charges retained in the node FG1 are distributedbetween the node FG1 and the node FG2, data voltage in the dataretention portion connected to the node FG1 is transferred to the dataretention portion connected to the node FG2. The wirings 4001 and 4003are set low. The wiring 4006 is set high. The wiring 4005 and thewirings 4007 to 4009 are set low. When the transistor 4200 is turned on,the electric charges in the node FG1 are distributed between the nodeFG1 and the node FG2.

Here, the potential after the electric charge distribution is decreasedfrom the written potential, “V_(D1)−V_(th).” Thus, the capacitance ofthe capacitor 4600 is preferably larger than the capacitance of thecapacitor 4500. Alternatively, the potential written to the node FG1,“V_(D1)−V_(th)”, is preferably larger than the potential correspondingto the same data, “V₁−V_(th).” By changing the ratio of the capacitancesand setting the written potential larger in advance as described above,a decrease in potential after the electric charge distribution can besuppressed. The change in potential due to the electric chargedistribution is described later.

Next, operation of reading data voltage to the data retention portionconnected to the node FG1 (hereinafter referred to as reading operation2) is described.

In the reading operation 2, the wiring 4003 which is brought into anelectrically floating state after precharge is discharged. The wirings4005 to 4008 are set low. The wiring 4009 is set high at the time ofprecharge and then, set low. When the wiring 4009 is set low, thepotential of the node FG2 which is electrically floating is set at“V_(D1)−V_(th).” The potential of the node FG2 is decreased, so that acurrent flows through the transistor 4100. The current flows, so thatthe potential of the wiring 4003 which is electrically floating isdecreased. As the potential of the wiring 4003 is decreased, V_(gs) ofthe transistor 4100 is decreased. When V_(gs) of the transistor 4100becomes V_(th) of the transistor 4100, the current flowing through thetransistor 4100 is decreased. In other words, the potential of thewiring 4003 becomes “V_(D1)” which is larger than the potential of thenode FG2, “V_(D1)−V_(th),” by V_(th). The potential of the wiring 4003corresponds to the data voltage of the data retention portion connectedto the node FG1. The data voltage of the read analog value is subjectedto A/D conversion, so that data of the data retention portion connectedto the node FG1 is obtained. The above is the reading operation of thedata voltage of the data retention portion connected to the node FG1.

In other words, the wiring 4003 after precharge is brought into afloating state and the potential of the wiring 4009 is changed from highto low, whereby a current flows through the transistor 4100. When thecurrent flows, the potential of the wiring 4003 which is in a floatingstate is decreased to be “V_(D1).” In the transistor 4100, V_(gs)between “V_(D1)−V_(th)” of the node FG2 and “V_(D1)” of the wiring 4003becomes V_(th), so that the current stops. Then, “V_(D1)” written in thewriting operation 1 is read to the wiring 4003.

In the above-described reading operation of data voltages from the nodesFG1 and FG2, the data voltages can be read from the plurality of dataretention portions. For example, 4-bit (16-level) data is retained ineach of the node FG1 and the node FG2, whereby 8-bit (256-level) datacan be retained in total. Although the first to third layers 4021 to4023 are provided in the structure illustrated in FIG. 41, the storagecapacity can be increased by adding layers without increasing the areaof the semiconductor device.

The read potential can be read as a voltage larger than the written datavoltage by V_(th). Therefore, V_(th) of “V_(D1)−V_(th)” and V_(th) of“V_(D2)−V_(th)” written in the writing operation can be canceled to beread. As a result, the memory capacity per memory cell can be improvedand read data can be close to accurate data; thus, the data reliabilitybecomes excellent.

FIG. 42 is a cross-sectional view of a semiconductor device thatcorresponds to FIG. 41. The semiconductor device illustrated in FIG. 42includes the transistors 4100, 4200, 4300, and 4400 and the capacitors4500 and 4600. Here, the transistor 4100 is formed in the first layer4021, the transistors 4200 and 4300 and the capacitor 4500 are formed inthe second layer 4022, and the transistor 4400 and the capacitor 4600are formed in the third layer 4023.

Here, the description of the transistor 3300 can be referred to for thetransistors 4200, 4300, and 4400, and the description of the transistor3200 can be referred to for the transistor 4100. The description madewith reference to FIG. 38 can be appropriately referred to for otherwirings, other insulators, and the like.

Note that the capacitors 4500 and 4600 are formed by including theconductive layers each having a trench-like shape, while the conductivelayer of the capacitor 3400 in the semiconductor device in FIG. 38 isparallel to the substrate. With this structure, a larger capacity can beobtained without increasing the occupation area.

<FPGA>

One embodiment of the present invention can also be applied to an LSIsuch as a field programmable gate array (FPGA).

FIG. 43A illustrates an example of a block diagram of an FPGA. The FPGAincludes a routing switch element 521 and a logic element 522. The logicelement 522 can switch functions of a logic circuit, such as acombination circuit or a sequential circuit, in accordance withconfiguration data stored in a configuration memory.

FIG. 43B is a schematic view illustrating a function of the routingswitch element 521. The routing switch element 521 can switch aconnection between the logic elements 522 in accordance withconfiguration data stored in a configuration memory 523. Note thatalthough FIG. 43B illustrates one switch which switches a connectionbetween a terminal IN and a terminal OUT, in an actual FPGA, a pluralityof switches are provided between a plurality of the logic elements 522.

FIG. 43C illustrates a configuration example of a circuit serving as theconfiguration memory 523. The configuration memory 523 includes atransistor M11 that is an OS transistor and a transistor M12 that is asilicon (Si) transistor. Configuration data D_(SW) is supplied to a nodeFN_(SW) through the transistor M11. A potential of the configurationdata D_(SW) can be retained by turning off the transistor M11. The onand off states of the transistor M12 can be switched depending on thepotential of the retained configuration data D_(SW), so that theconnection between the terminal IN and the terminal OUT can be switched.

FIG. 43D is a schematic view illustrating a function of the logicelement 522. The logic element 522 can switch a potential of a terminalOUT_(mem) in accordance with configuration data stored in aconfiguration memory 527. A lookup table 524 can switch functions of acombination circuit that processes a signal of the terminal IN inaccordance with the potential of the terminal OUT_(mem). The logicelement 522 includes a register 525 that is a sequential circuit and aselector 526 that switches signals of the terminal OUT. The selector 526can select to output a signal of the lookup table 524 or to output asignal of the register 525 in accordance with the potential of theterminal OUT_(mem), which is output from the configuration memory 527.

FIG. 43E illustrates configuration example of a circuit serving as theconfiguration memory 527. The configuration memory 527 includes atransistor M13 and a transistor M14 that are OS transistors, and atransistor M15 and a transistor M16 that are Si transistors.Configuration data D_(LE) is supplied to a node FN_(LE) through thetransistor M13. Configuration data DB_(LE) is supplied to a nodeFNB_(LE) through the transistor M14. The configuration data DB_(LE)corresponds to a potential of the configuration data D_(LE) whose logicis inverted. The potential of the configuration data D_(LE) and thepotential of the configuration data DB_(LE) can be retained by turningoff the transistor M13 and the transistor M14, respectively. The on andoff states of one of the transistors M15 and M16 are switched inaccordance with the retained potentials of the configuration data D_(LE)and the configuration data DB_(LE), so that a potential VDD or apotential VS S can be supplied to the terminal OUT_(mem).

For the configuration illustrated in FIGS. 43A to 43E, any of thestructures described in the above embodiment can be used. For example,Si transistors are used as the transistors M12, M15, and M16, and OStransistors are used as the transistors M11, M13, and M14. In this case,a wiring for connecting the Si transistors provided in a lower layer canbe formed with a low-resistance conductive material. Therefore, acircuit with high access speed and low power consumption can beobtained.

The structures described in this embodiment can be used in appropriatecombination with any of the structures described in the otherembodiments.

Embodiment 13

In this embodiment, an example of an imaging device including thetransistor or the like of one embodiment of the present invention willbe described.

<Configuration of Imaging Device>

FIG. 44A is a plan view illustrating an example of an imaging device 200of one embodiment of the present invention. The imaging device 200includes a pixel portion 210 and peripheral circuits for driving thepixel portion 210 (a peripheral circuit 260, a peripheral circuit 270, aperipheral circuit 280, and a peripheral circuit 290). The pixel portion210 includes a plurality of pixels 211 arranged in a matrix with p rowsand q columns (p and q are each an integer of 2 or more). The peripheralcircuit 260, the peripheral circuit 270, the peripheral circuit 280, andthe peripheral circuit 290 are each connected to the plurality of pixels211, and a signal for driving the plurality of pixels 211 is supplied.In this specification and the like, in some cases, a “peripheralcircuit” or a “driver circuit” indicate all of the peripheral circuits260, 270, 280, and 290. For example, the peripheral circuit 260 can beregarded as part of the peripheral circuit.

The imaging device 200 preferably includes a light source 291. The lightsource 291 can emit detection light P1.

The peripheral circuit includes at least one of a logic circuit, aswitch, a buffer, an amplifier circuit, and a converter circuit. Theperipheral circuit may be formed over a substrate where the pixelportion 210 is formed. Alternatively, a semiconductor device such as anIC chip may be used as part or the whole of the peripheral circuit. Notethat as the peripheral circuit, one or more of the peripheral circuits260, 270, 280, and 290 may be omitted.

As illustrated in FIG. 44B, the pixels 211 may be provided to beinclined in the pixel portion 210 included in the imaging device 200.When the pixels 211 are obliquely arranged, the distance between pixels(pitch) can be shortened in the row direction and the column direction.Accordingly, the quality of an image taken with the imaging device 200can be improved.

<Configuration Example 1 of Pixel>

The pixel 211 included in the imaging device 200 is formed with aplurality of subpixels 212, and each subpixel 212 is combined with afilter (color filter) which transmits light in a specific wavelengthrange, whereby data for achieving color image display can be obtained.

FIG. 45A is a top view showing an example of the pixel 211 with which acolor image is obtained. The pixel 211 illustrated in FIG. 45A includesa subpixel 212 provided with a color filter that transmits light in ared (R) wavelength range (also referred to as a subpixel 212R), asubpixel 212 provided with a color filter that transmits light in agreen (G) wavelength range (also referred to as a subpixel 212G), and asubpixel 212 provided with a color filter that transmits light in a blue(B) wavelength range (also referred to as a subpixel 212B). The subpixel212 can function as a photosensor.

The subpixel 212 (the subpixel 212R, the subpixel 212G, and the subpixel212B) is electrically connected to a wiring 231, a wiring 247, a wiring248, a wiring 249, and a wiring 250. In addition, the subpixel 212R, thesubpixel 212G, and the subpixel 212B are connected to respective wirings253 which are independently provided. In this specification and thelike, for example, the wiring 248 and the wiring 249 that are connectedto the pixel 211 in the n-th row are referred to as a wiring 248[n] anda wiring 249[n]. For example, the wiring 253 connected to the pixel 211in the m-th column is referred to as a wiring 253[m]. Note that in FIG.45A, the wirings 253 connected to the subpixel 212R, the subpixel 212G,and the subpixel 212B in the pixel 211 in the m-th column are referredto as a wiring 253[m]R, a wiring 253[m]G, and a wiring 253[m]B. Thesubpixels 212 are electrically connected to the peripheral circuitthrough the above wirings.

The imaging device 200 has a structure in which the subpixel 212 iselectrically connected to the subpixel 212 in an adjacent pixel 211which is provided with a color filter transmitting light in the samewavelength range as the subpixel 212, via a switch. FIG. 45B shows aconnection example of the subpixels 212: the subpixel 212 in the pixel211 arranged in the n-th (n is an integer greater than or equal to 1 andless than or equal top) row and the m-th (m is an integer greater thanor equal to 1 and less than or equal to q) column and the subpixel 212in the adjacent pixel 211 arranged in an (n+1)-th row and the m-thcolumn In FIG. 45B, the subpixel 212R arranged in the n-th row and them-th column and the subpixel 212R arranged in the (n+1)-th row and them-th column are connected to each other via a switch 201. The subpixel212G arranged in the n-th row and the m-th column and the subpixel 212Garranged in the (n+1)-th row and the m-th column are connected to eachother via a switch 202. The subpixel 212B arranged in the n-th row andthe m-th column and the subpixel 212B arranged in the (n+1)-th row andthe m-th column are connected to each other via a switch 203.

The color filter used in the subpixel 212 is not limited to red (R),green (G), and blue (B) color filters, and color filters that transmitlight of cyan (C), yellow (Y), and magenta (M) may be used. By provisionof the subpixels 212 that sense light in three different wavelengthranges in one pixel 211, a full-color image can be obtained.

The pixel 211 including the subpixel 212 provided with a color filtertransmitting yellow (Y) light may be provided, in addition to thesubpixels 212 provided with the color filters transmitting red (R),green (G), and blue (B) light. The pixel 211 including the subpixel 212provided with a color filter transmitting blue (B) light may beprovided, in addition to the subpixels 212 provided with the colorfilters transmitting cyan (C), yellow (Y), and magenta (M) light. Whenthe subpixels 212 sensing light in four different wavelength ranges areprovided in one pixel 211, the reproducibility of colors of an obtainedimage can be increased.

For example, in FIG. 45A, in regard to the subpixel 212 sensing light ina red wavelength range, the subpixel 212 sensing light in a greenwavelength range, and the subpixel 212 sensing light in a bluewavelength range, the pixel number ratio (or the light receiving arearatio) thereof is not necessarily 1:1:1. For example, the Bayerarrangement in which the pixel number ratio (the light receiving arearatio) is set at red:green:blue=1:2:1 may be employed. Alternatively,the pixel number ratio (the light receiving area ratio) of red and greento blue may be 1:6:1.

Although the number of subpixels 212 provided in the pixel 211 may beone, two or more subpixels are preferably provided. For example, whentwo or more subpixels 212 sensing light in the same wavelength range areprovided, the redundancy is increased, and the reliability of theimaging device 200 can be increased.

When an infrared (IR) filter that transmits infrared light and absorbsor reflects visible light is used as the filter, the imaging device 200that senses infrared light can be achieved.

Furthermore, when a neutral density (ND) filter (dark filter) is used,output saturation which occurs when a large amount of light enters aphotoelectric conversion element (light-receiving element) can beprevented. With a combination of ND filters with different dimmingcapabilities, the dynamic range of the imaging device can be increased.

Besides the above-described filter, the pixel 211 may be provided with alens. An arrangement example of the pixel 211, a filter 254, and a lens255 is described with cross-sectional views in FIGS. 46A and 46B. Withthe lens 255, the photoelectric conversion element can receive incidentlight efficiently. Specifically, as illustrated in FIG. 46A, light 256enters a photoelectric conversion element 220 through the lens 255, thefilter 254 (a filter 254R, a filter 254G, and a filter 254B), a pixelcircuit 230, and the like which are provided in the pixel 211.

As indicated by a region surrounded with dashed double-dotted lines,however, part of the light 256 indicated by arrows might be blocked bysome wirings 257. Thus, a preferable structure is such that the lens 255and the filter 254 are provided on the photoelectric conversion element220 side as illustrated in FIG. 46B, whereby the photoelectricconversion element 220 can efficiently receive the light 256. When thelight 256 enters the photoelectric conversion element 220 from thephotoelectric conversion element 220 side, the imaging device 200 withhigh sensitivity can be provided.

As the photoelectric conversion element 220 illustrated in FIGS. 46A and46B, a photoelectric conversion element in which a p-n junction or ap-i-n junction is formed may be used.

The photoelectric conversion element 220 may be formed using a substancethat has a function of absorbing a radiation and generating electriccharges. Examples of the substance that has a function of absorbing aradiation and generating electric charges include selenium, lead iodide,mercury iodide, gallium arsenide, cadmium telluride, and cadmium zincalloy.

For example, when selenium is used for the photoelectric conversionelement 220, the photoelectric conversion element 220 can have a lightabsorption coefficient in a wide wavelength range, such as visiblelight, ultraviolet light, infrared light, X-rays, and gamma rays.

One pixel 211 included in the imaging device 200 may include thesubpixel 212 with a first filter in addition to the subpixel 212illustrated in FIGS. 45A and 45B.

<Configuration Example 2 of Pixel>

An example of a pixel including a transistor using silicon and atransistor using an oxide semiconductor will be described below.

FIGS. 47A and 47B are each a cross-sectional view of an element includedin an imaging device. The imaging device illustrated in FIG. 47Aincludes a transistor 351 including silicon over a silicon substrate300, transistors 352 and 353 which include an oxide semiconductor andare stacked over the transistor 351, and a photodiode 360 provided in asilicon substrate 300. The transistors and the photodiode 360 areelectrically connected to various plugs 370 and wirings 371. Inaddition, an anode 361 of the photodiode 360 is electrically connectedto the plug 370 through a low-resistance region 363.

The imaging device includes a layer 310 including the transistor 351provided on the silicon substrate 300 and the photodiode 360 provided inthe silicon substrate 300, a layer 320 which is in contact with thelayer 310 and includes the wirings 371, a layer 330 which is in contactwith the layer 320 and includes the transistors 352 and 353, and a layer340 which is in contact with the layer 330 and includes a wiring 372 anda wiring 373.

In the example of cross-sectional view in FIG. 47A, a light-receivingsurface of the photodiode 360 is provided on the side opposite to asurface of the silicon substrate 300 where the transistor 351 is formed.With this structure, a light path can be secured without an influence ofthe transistors and the wirings. Thus, a pixel with a high apertureratio can be formed. Note that the light-receiving surface of thephotodiode 360 can be the same as the surface where the transistor 351is formed.

In the case where a pixel is formed with use of only transistors usingan oxide semiconductor, the layer 310 may include the transistor usingan oxide semiconductor. Alternatively, the layer 310 may be omitted, andthe pixel may include only transistors using an oxide semiconductor.

In the case where a pixel is formed with use of only transistors usingsilicon, the layer 330 may be omitted. An example of a cross-sectionalview in which the layer 330 is not provided is shown in FIG. 47B.

Note that the silicon substrate 300 may be an SOI substrate.Furthermore, the silicon substrate 300 can be replaced with a substratemade of germanium, silicon germanium, silicon carbide, gallium arsenide,aluminum gallium arsenide, indium phosphide, gallium nitride, or anorganic semiconductor.

Here, an insulator 380 is provided between the layer 310 including thetransistor 351 and the photodiode 360 and the layer 330 including thetransistors 352 and 353. However, there is no limitation on the positionof the insulator 380.

Hydrogen in an insulator provided in the vicinity of a channel formationregion of the transistor 351 terminates dangling bonds of silicon;accordingly, the reliability of the transistor 351 can be improved. Incontrast, hydrogen in the insulator provided in the vicinity of thetransistor 352, the transistor 353, and the like becomes one of factorsgenerating a carrier in the oxide semiconductor. Thus, the hydrogen maycause a reduction of the reliability of the transistor 352, thetransistor 353, and the like. Therefore, in the case where thetransistor using an oxide semiconductor is provided over the transistorusing a silicon-based semiconductor, it is preferable that the insulator380 having a function of blocking hydrogen be provided between thetransistors. When the hydrogen is confined below the insulator 380, thereliability of the transistor 351 can be improved. In addition, thehydrogen can be prevented from being diffused from a part below theinsulator 380 to a part above the insulator 380; thus, the reliabilityof the transistor 352, the transistor 353, and the like can beincreased.

As the insulator 380, an insulator having a function of blocking oxygenor hydrogen is used, for example.

In the cross-sectional view in FIG. 47A, the photodiode 360 in the layer310 and the transistor in the layer 330 can be formed so as to overlapwith each other. Thus, the degree of integration of pixels can beincreased. In other words, the resolution of the imaging device can beincreased.

As illustrated in FIG. 48A1 and FIG. 48B1, part or the whole of theimaging device can be bent. FIG. 48A1 illustrates a state in which theimaging device is bent in the direction of a dashed-dotted line X1-X2.FIG. 48A2 is a cross-sectional view illustrating a portion indicated bythe dashed-dotted line X1-X2 in FIG. 48A1. FIG. 48A3 is across-sectional view illustrating a portion indicated by a dashed-dottedline Y1-Y2 in FIG. 48A1.

FIG. 48B1 illustrates a state where the imaging device is bent in thedirection of a dashed-dotted line X3-X4 and the direction of adashed-dotted line Y3-Y4. FIG. 48B2 is a cross-sectional viewillustrating a portion indicated by the dashed-dotted line X3-X4 in FIG.48B1. FIG. 48B3 is a cross-sectional view illustrating a portionindicated by the dashed-dotted line Y3-Y4 in FIG. 48B1.

The bent imaging device enables the curvature of field and astigmatismto be reduced. Thus, the optical design of lens and the like, which isused in combination of the imaging device, can be facilitated. Forexample, the number of lenses used for aberration correction can bereduced; accordingly, a reduction of size or weight of electronicdevices using the imaging device, and the like, can be achieved. Inaddition, the quality of a captured image can be improved.

The structures described in this embodiment can be used in appropriatecombination with any of the structures described in the otherembodiments.

Embodiment 14

In this embodiment, examples of CPUs including semiconductor devicessuch as the transistor of one embodiment of the present invention andthe above-described memory device will be described.

<Configuration of CPU>

FIG. 49 is a block diagram illustrating a configuration example of a CPUincluding any of the above-described transistors as a component.

The CPU illustrated in FIG. 49 includes, over a substrate 1190, anarithmetic logic unit (ALU) 1191, an ALU controller 1192, an instructiondecoder 1193, an interrupt controller 1194, a timing controller 1195, aregister 1196, a register controller 1197, a bus interface 1198, arewritable ROM 1199, and a ROM interface 1189. A semiconductorsubstrate, an SOI substrate, a glass substrate, or the like is used asthe substrate 1190. The ROM 1199 and the ROM interface 1189 may beprovided over a separate chip. Needless to say, the CPU in FIG. 49 isjust an example in which the configuration has been simplified, and anactual CPU may have a variety of configurations depending on theapplication. For example, the CPU may have the following configuration:a structure including the CPU illustrated in FIG. 49 or an arithmeticcircuit is considered as one core; a plurality of such cores areincluded; and the cores operate in parallel. The number of bits that theCPU can process in an internal arithmetic circuit or in a data bus canbe 8, 16, 32, or 64, for example.

An instruction that is input to the CPU through the bus interface 1198is input to the instruction decoder 1193 and decoded therein, and then,input to the ALU controller 1192, the interrupt controller 1194, theregister controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the registercontroller 1197, and the timing controller 1195 conduct various controlsin accordance with the decoded instruction. Specifically, the ALUcontroller 1192 generates signals for controlling the operation of theALU 1191. While the CPU is executing a program, the interrupt controller1194 judges an interrupt request from an external input/output device ora peripheral circuit on the basis of its priority or a mask state, andprocesses the request. The register controller 1197 generates an addressof the register 1196, and reads/writes data from/to the register 1196 inaccordance with the state of the CPU.

The timing controller 1195 generates signals for controlling operationtimings of the ALU 1191, the ALU controller 1192, the instructiondecoder 1193, the interrupt controller 1194, and the register controller1197. For example, the timing controller 1195 includes an internal clockgenerator for generating an internal clock signal based on a referenceclock signal, and supplies the internal clock signal to the abovecircuits.

In the CPU illustrated in FIG. 49, a memory cell is provided in theregister 1196. For the memory cell of the register 1196, any of theabove-described transistors, the above-described memory device, or thelike can be used.

In the CPU illustrated in FIG. 49, the register controller 1197 selectsoperation of retaining data in the register 1196 in accordance with aninstruction from the ALU 1191. That is, the register controller 1197selects whether data is retained by a flip-flop or by a capacitor in thememory cell included in the register 1196. When data retention by theflip-flop is selected, a power supply voltage is supplied to the memorycell in the register 1196. When data retention by the capacitor isselected, the data is rewritten in the capacitor, and supply of a powersupply voltage to the memory cell in the register 1196 can be stopped.

FIG. 50 is an example of a circuit diagram of a memory element 1200 thatcan be used as the register 1196. The memory element 1200 includes acircuit 1201 in which stored data is volatile when power supply isstopped, a circuit 1202 in which stored data is nonvolatile even whenpower supply is stopped, a switch 1203, a switch 1204, a logic element1206, a capacitor 1207, and a circuit 1220 having a selecting function.The circuit 1202 includes a capacitor 1208, a transistor 1209, and atransistor 1210. Note that the memory element 1200 may further includeanother element such as a diode, a resistor, or an inductor, as needed.

Here, the above-described memory device can be used as the circuit 1202.When supply of a power supply voltage to the memory element 1200 isstopped, GND (0 V) or a potential at which the transistor 1209 in thecircuit 1202 is turned off continues to be input to a gate of thetransistor 1209. For example, the gate of the transistor 1209 isgrounded through a load such as a resistor.

Shown here is an example in which the switch 1203 is a transistor 1213having one conductivity type (e.g., an n-channel transistor) and theswitch 1204 is a transistor 1214 having a conductivity type opposite tothe one conductivity type (e.g., a p-channel transistor). A firstterminal of the switch 1203 corresponds to one of a source and a drainof the transistor 1213, a second terminal of the switch 1203 correspondsto the other of the source and the drain of the transistor 1213, andconduction or non-conduction between the first terminal and the secondterminal of the switch 1203 (i.e., the on/off state of the transistor1213) is selected by a control signal RD input to a gate of thetransistor 1213. A first terminal of the switch 1204 corresponds to oneof a source and a drain of the transistor 1214, a second terminal of theswitch 1204 corresponds to the other of the source and the drain of thetransistor 1214, and conduction or non-conduction between the firstterminal and the second terminal of the switch 1204 (i.e., the on/offstate of the transistor 1214) is selected by the control signal RD inputto a gate of the transistor 1214.

One of a source and a drain of the transistor 1209 is electricallyconnected to one of a pair of electrodes of the capacitor 1208 and agate of the transistor 1210. Here, the connection portion is referred toas a node M2. One of a source and a drain of the transistor 1210 iselectrically connected to a line which can supply a low power supplypotential (e.g., a GND line), and the other thereof is electricallyconnected to the first terminal of the switch 1203 (the one of thesource and the drain of the transistor 1213). The second terminal of theswitch 1203 (the other of the source and the drain of the transistor1213) is electrically connected to the first terminal of the switch 1204(the one of the source and the drain of the transistor 1214). The secondterminal of the switch 1204 (the other of the source and the drain ofthe transistor 1214) is electrically connected to a line which cansupply a power supply potential VDD. The second terminal of the switch1203 (the other of the source and the drain of the transistor 1213), thefirst terminal of the switch 1204 (the one of the source and the drainof the transistor 1214), an input terminal of the logic element 1206,and one of a pair of electrodes of the capacitor 1207 are electricallyconnected to each other. Here, the connection portion is referred to asa node M1. The other of the pair of electrodes of the capacitor 1207 canbe supplied with a constant potential. For example, the other of thepair of electrodes of the capacitor 1207 can be supplied with a lowpower supply potential (e.g., GND) or a high power supply potential(e.g., VDD). The other of the pair of electrodes of the capacitor 1207is electrically connected to the line which can supply a low powersupply potential (e.g., a GND line). The other of the pair of electrodesof the capacitor 1208 can be supplied with a constant potential. Forexample, the other of the pair of electrodes of the capacitor 1208 canbe supplied with the low power supply potential (e.g., GND) or the highpower supply potential (e.g., VDD). The other of the pair of electrodesof the capacitor 1208 is electrically connected to the line which cansupply a low power supply potential (e.g., a GND line).

The capacitor 1207 and the capacitor 1208 are not necessarily providedas long as the parasitic capacitance of the transistor, the wiring, orthe like is actively utilized.

A control signal WE is input to the gate of the transistor 1209. As foreach of the switch 1203 and the switch 1204, a conduction state or anon-conduction state between the first terminal and the second terminalis selected by the control signal RD which is different from the controlsignal WE. When the first terminal and the second terminal of one of theswitches are in the conduction state, the first terminal and the secondterminal of the other of the switches are in the non-conduction state.

A signal corresponding to data retained in the circuit 1201 is input tothe other of the source and the drain of the transistor 1209. FIG. 50illustrates an example in which a signal output from the circuit 1201 isinput to the other of the source and the drain of the transistor 1209.The logic value of a signal output from the second terminal of theswitch 1203 (the other of the source and the drain of the transistor1213) is inverted by the logic element 1206, and the inverted signal isinput to the circuit 1201 through the circuit 1220.

In the example of FIG. 50, a signal output from the second terminal ofthe switch 1203 (the other of the source and the drain of the transistor1213) is input to the circuit 1201 through the logic element 1206 andthe circuit 1220; however, one embodiment of the present invention isnot limited thereto. The signal output from the second terminal of theswitch 1203 (the other of the source and the drain of the transistor1213) may be input to the circuit 1201 without its logic value beinginverted. For example, in the case where the circuit 1201 includes anode in which a signal obtained by inversion of the logic value of asignal input from the input terminal is retained, the signal output fromthe second terminal of the switch 1203 (the other of the source and thedrain of the transistor 1213) can be input to the node.

In FIG. 50, the transistors included in the memory element 1200 exceptthe transistor 1209 can each be a transistor in which a channel isformed in a film formed using a semiconductor other than an oxidesemiconductor or in the substrate 1190. For example, the transistor canbe a transistor whose channel is formed in a silicon film or a siliconsubstrate. Alternatively, all the transistors in the memory element 1200may be a transistor in which a channel is formed in an oxidesemiconductor. Further alternatively, in the memory element 1200, atransistor in which a channel is formed in an oxide semiconductor may beincluded besides the transistor 1209, and a transistor in which achannel is formed in a layer formed using a semiconductor other than anoxide semiconductor or in the substrate 1190 can be used for the rest ofthe transistors.

As the circuit 1201 in FIG. 50, for example, a flip-flop circuit can beused. As the logic element 1206, for example, an inverter or a clockedinverter can be used.

In a period during which the memory element 1200 is not supplied withthe power supply voltage, the semiconductor device of one embodiment ofthe present invention can retain data stored in the circuit 1201 by thecapacitor 1208 which is provided in the circuit 1202.

The off-state current of a transistor in which a channel is formed in anoxide semiconductor is extremely low. For example, the off-state currentof a transistor in which a channel is formed in an oxide semiconductoris significantly lower than that of a transistor in which a channel isformed in silicon having crystallinity. Thus, when the transistor isused as the transistor 1209, a signal held in the capacitor 1208 isretained for a long time also in a period during which the power supplyvoltage is not supplied to the memory element 1200. The memory element1200 can accordingly retain the stored content (data) also in a periodduring which the supply of the power supply voltage is stopped.

Since the above-described memory element performs pre-charge operationwith the switch 1203 and the switch 1204, the time required for thecircuit 1201 to retain original data again after the supply of the powersupply voltage is restarted can be shortened.

In the circuit 1202, a signal retained by the capacitor 1208 is input tothe gate of the transistor 1210. Therefore, after supply of the powersupply voltage to the memory element 1200 is restarted, the signalretained by the capacitor 1208 can be converted into the onecorresponding to the state (the on state or the off state) of thetransistor 1210 to be read from the circuit 1202. Consequently, anoriginal signal can be accurately read even when a potentialcorresponding to the signal retained by the capacitor 1208 varies tosome degree.

By applying the above-described memory element 1200 to a memory devicesuch as a register or a cache memory included in a processor, data inthe memory device can be prevented from being lost owing to the stop ofthe supply of the power supply voltage. Furthermore, shortly after thesupply of the power supply voltage is restarted, the memory device canbe returned to the same state as that before the power supply isstopped. Therefore, the power supply can be stopped even for a shorttime in the processor or one or a plurality of logic circuits includedin the processor, resulting in lower power consumption.

Although the memory element 1200 is used in a CPU, the memory element1200 can also be used in an LSI such as a digital signal processor (DSP)or a custom LSI, and a radio frequency (RF) device. The memory element1200 can also be used in an LSI such as a programmable logic circuitincluding a field programmable gate array (FPGA) or a complexprogrammable logic device (CPLD).

The structures described in this embodiment can be used in appropriatecombination with any of the structures described in the otherembodiments.

Embodiment 15

In this embodiment, display devices each including the transistor or thelike of one embodiment of the present invention will be described withreference to FIGS. 51A to 51C and FIGS. 52A and 52B.

<Configuration of Display Device>

Examples of a display element provided in the display device include aliquid crystal element (also referred to as a liquid crystal displayelement) and a light-emitting element (also referred to as alight-emitting display element). The light-emitting element includes, inits category, an element whose luminance is controlled by a current orvoltage, and specifically includes, in its category, an inorganicelectroluminescent (EL) element, an organic EL element, and the like. Adisplay device including an EL element (EL display device) and a displaydevice including a liquid crystal element (liquid crystal displaydevice) are described below as examples of the display device.

Note that the display device described below includes in its category apanel in which a display element is sealed and a module in which an ICsuch as a controller is mounted on the panel.

The display device described below refers to an image display device ora light source (including a lighting device). The display deviceincludes any of the following modules: a module provided with aconnector such as an FPC or TCP; a module in which a printed wiringboard is provided at the end of TCP; and a module in which an integratedcircuit (IC) is mounted directly on a display element by a COG method.

FIGS. 51A to 51C illustrate an example of an EL display device of oneembodiment of the present invention. FIG. 51A is a circuit diagram of apixel in an EL display device. FIG. 51B is a plan view showing the wholeof the EL display device. FIG. 51C is a cross-sectional view taken alongpart of dashed-dotted line M-N in FIG. 51B.

FIG. 51A illustrates an example of a circuit diagram of a pixel used inan EL display device.

Note that in this specification and the like, it might be possible forthose skilled in the art to constitute one embodiment of the inventioneven when portions to which all the terminals of an active element(e.g., a transistor or a diode), a passive element (e.g., a capacitor ora resistor), or the like are connected are not specified. In otherwords, one embodiment of the invention can be clear even when connectionportions are not specified. Furthermore, in the case where a connectionportion is disclosed in this specification and the like, it can bedetermined that one embodiment of the invention in which a connectionportion is not specified is disclosed in this specification and thelike, in some cases. Particularly in the case where the number ofportions to which a terminal is connected might be more than one, it isnot necessary to specify the portions to which the terminal isconnected. Therefore, it might be possible to constitute one embodimentof the invention by specifying only portions to which some of terminalsof an active element (e.g., a transistor or a diode), a passive element(e.g., a capacitor or a resistor), or the like are connected.

Note that in this specification and the like, it might be possible forthose skilled in the art to specify the invention when at least theconnection portion of a circuit is specified. Alternatively, it might bepossible for those skilled in the art to specify the invention when atleast a function of a circuit is specified. In other words, when afunction of a circuit is specified, one embodiment of the presentinvention can be clear. Furthermore, it can be determined that oneembodiment of the present invention whose function is specified isdisclosed in this specification and the like in some cases. Therefore,when a connection portion of a circuit is specified, the circuit isdisclosed as one embodiment of the invention even when a function is notspecified, and one embodiment of the invention can be constituted.Alternatively, when a function of a circuit is specified, the circuit isdisclosed as one embodiment of the invention even when a connectionportion is not specified, and one embodiment of the invention can beconstituted.

The EL display device illustrated in FIG. 51A includes a switchingelement 743, a transistor 741, a capacitor 742, and a light-emittingelement 719.

Note that FIG. 51A and the like each illustrate an example of a circuitstructure; therefore, a transistor can be provided additionally. Incontrast, for each node in FIG. 51A, it is possible not to provide anadditional transistor, switch, passive element, or the like.

A gate of the transistor 741 is electrically connected to one terminalof the switching element 743 and one electrode of the capacitor 742. Asource of the transistor 741 is electrically connected to the otherelectrode of the capacitor 742 and one electrode of the light-emittingelement 719. A drain of the transistor 741 is supplied with a powersupply potential VDD. The other terminal of the switching element 743 iselectrically connected to a signal line 744. A constant potential issupplied to the other electrode of the light-emitting element 719. Theconstant potential is a ground potential GND or a potential lower thanthe ground potential GND.

It is preferable to use a transistor as the switching element 743. Whenthe transistor is used as the switching element, the area of a pixel canbe reduced, so that the EL display device can have high resolution. Asthe switching element 743, a transistor formed through the same step asthe transistor 741 can be used, so that EL display devices can bemanufactured with high productivity. Note that as the transistor 741and/or the switching element 743, any of the above-described transistorscan be used, for example.

FIG. 51B is a plan view of the EL display device. The EL display deviceincludes a substrate 700, a substrate 750, a sealant 734, a drivercircuit 735, a driver circuit 736, a pixel 737, and an FPC 732. Thesealant 734 is provided between the substrate 700 and the substrate 750so as to surround the pixel 737, the driver circuit 735, and the drivercircuit 736. Note that the driver circuit 735 and/or the driver circuit736 may be provided outside the sealant 734.

FIG. 51C is a cross-sectional view of the EL display device taken alongpart of dashed-dotted line M-N in FIG. 51B.

The transistor 741 in FIG. 51C includes an insulator 701 over thesubstrate 700; a conductor 702 a over the insulator 701; an insulator703 in which the conductor 702 a is embedded; an insulator 704 over theinsulator 703; a semiconductor 705 over the insulator 704; a conductor708 and an insulator 706 over the semiconductor 705; an insulator 707over the insulator 706; and a conductor 709 over the insulator 707. Notethat the structure of the transistor 741 is just an example; thetransistor 741 may have a structure different from that illustrated inFIG. 51C.

Thus, in the transistor 741 illustrated in FIG. 51C, the conductor 702 afunctions as a gate electrode, the insulator 703 and the insulator 707each function as a gate insulator, the conductor 708 functions as asource electrode or a drain electrode, and the conductor 709 functionsas a gate electrode. Note that in some cases, electrical characteristicsof the semiconductor 705 change if light enters the semiconductor 705.To prevent this, it is preferable that one or more of the conductor 702a and the conductor 709 have a light-blocking property.

FIG. 51C illustrates the capacitor 742 that includes a conductor 702 bover the insulator 701, the insulator 703 over the conductor 702 b, andthe conductor 708 over the insulator 703.

In the capacitor 742, the conductor 702 b functions as one electrode,and the conductor 708 functions as the other electrode.

Thus, the capacitor 742 can be formed using a film of the transistor741. The conductor 702 a and the conductor 702 b are preferablyconductors of the same kind, in which case the conductor 702 a and theconductor 702 b can be formed through the same step. Furthermore, theconductor 707 a and the conductor 707 b are preferably conductors of thesame kind, in which case the conductor 707 a and the conductor 707 b canbe formed through the same step.

The capacitor 742 illustrated in FIG. 51C has a large capacitance perarea occupied by the capacitor. Therefore, the EL display deviceillustrated in FIG. 51C has high display quality.

An insulator 720 is provided over the transistor 741 and the capacitor742. Here, the insulator 716 and the insulator 720 may have an openingportion reaching the region 705 a that serves as the source of thetransistor 741. A conductor 781 is provided over the insulator 720. Theconductor 781 is electrically connected to the transistor 741 throughthe opening in the insulator 720.

A partition wall 784 having an opening reaching the conductor 781 isprovided over the conductor 781. A light-emitting layer 782 in contactwith the conductor 781 through the opening provided in the partitionwall 784 is provided over the partition wall 784. A conductor 783 isprovided over the light-emitting layer 782. A region where the conductor781, the light-emitting layer 782, and the conductor 783 overlap withone another functions as the light-emitting element 719.

So far, examples of the EL display device are described. Next, anexample of a liquid crystal display device is described.

FIG. 52A is a circuit diagram illustrating a configuration example of apixel of a liquid crystal display device. A pixel shown in FIGS. 52A and52B includes a transistor 751, a capacitor 752, and an element (liquidcrystal element) 753 in which a space between a pair of electrodes isfilled with a liquid crystal.

One of a source and a drain of the transistor 751 is electricallyconnected to a signal line 755, and a gate of the transistor 751 iselectrically connected to a scan line 754.

One electrode of the capacitor 752 is electrically connected to theother of the source and the drain of the transistor 751, and the otherelectrode of the capacitor 752 is electrically connected to a wiring towhich a common potential is supplied.

One electrode of the liquid crystal element 753 is electricallyconnected to the other of the source and the drain of the transistor751, and the other electrode of the liquid crystal element 753 iselectrically connected to a wiring to which a common potential issupplied. The common potential supplied to the wiring electricallyconnected to the other electrode of the capacitor 752 may be differentfrom that supplied to the other electrode of the liquid crystal element753.

Note that the description of the liquid crystal display device is madeon the assumption that the plan view of the liquid crystal displaydevice is similar to that of the EL display device. FIG. 52B is across-sectional view of the liquid crystal display device taken alongdashed-dotted line M-N in FIG. 51B. In FIG. 52B, the FPC 732 isconnected to the wiring 733 a via the terminal 731. Note that the wiring733 a may be formed using the same kind of conductor as the conductor ofthe transistor 751 or using the same kind of semiconductor as thesemiconductor of the transistor 751.

For the transistor 751, the description of the transistor 741 isreferred to. For the capacitor 752, the description of the capacitor 742is referred to. Note that the structure of the capacitor 752 in FIG. 52Bcorresponds to, but is not limited to, the structure of the capacitor742 in FIG. 51C.

Note that in the case where an oxide semiconductor is used as thesemiconductor of the transistor 751, the off-state current of thetransistor 751 can be extremely small. Therefore, an electric chargeheld in the capacitor 752 is unlikely to leak, so that the voltageapplied to the liquid crystal element 753 can be maintained for a longtime. Accordingly, the transistor 751 can be kept off during a period inwhich moving images with few motions or a still image are/is displayed,whereby power for the operation of the transistor 751 can be saved inthat period; accordingly a liquid crystal display device with low powerconsumption can be provided. Furthermore, the area occupied by thecapacitor 752 can be reduced; thus, a liquid crystal display device witha high aperture ratio or a high-resolution liquid crystal display devicecan be provided.

An insulator 721 is provided over the transistor 751 and the capacitor752. The insulator 721 has an opening reaching the transistor 751. Aconductor 791 is provided over the insulator 721. The conductor 791 iselectrically connected to the transistor 751 through the opening in theinsulator 721.

An insulator 792 functioning as an alignment film is provided over theconductor 791. A liquid crystal layer 793 is provided over the insulator792. An insulator 794 functioning as an alignment film is provided overthe liquid crystal layer 793. A spacer 795 is provided over theinsulator 794. A conductor 796 is provided over the spacer 795 and theinsulator 794. A substrate 797 is provided over the conductor 796.

Note that the following methods can be employed for driving the liquidcrystal: a twisted nematic (TN) mode, a super twisted nematic (STN)mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS)mode, a multi-domain vertical alignment (MVA) mode, a patterned verticalalignment (PVA) mode, an advanced super view (ASV) mode, an axiallysymmetric aligned microcell (ASM) mode, an optically compensatedbirefringence (OCB) mode, an electrically controlled birefringence (ECB)mode, an ferroelectric liquid crystal (FLC) mode, an anti-ferroelectricliquid crystal (AFLC) mode, a polymer dispersed liquid crystal (PDLC)mode, a guest-host mode, and a blue phase mode. Note that the presentinvention is not limited to these examples, and various driving methodscan be used.

Owing to the above-described structure, a display device including acapacitor occupying a small area, a display device with high displayquality, or a high-resolution display device can be provided.

For example, in this specification and the like, a display element, adisplay device which is a device including a display element, alight-emitting element, and a light-emitting device which is a deviceincluding a light-emitting element can employ various modes or caninclude various elements. For example, the display element, the displaydevice, the light-emitting element, or the light-emitting deviceincludes at least one of a light-emitting diode (LED) for white, red,green, blue, or the like, a transistor (a transistor that emits lightdepending on current), an electron emitter, a liquid crystal element,electronic ink, an electrophoretic element, a grating light valve (GLV),a plasma display panel (PDP), a display element using micro electromechanical systems (MEMS), a digital micromirror device (DMD), a digitalmicro shutter (DMS), an interferometric modulator display (IMOD)element, a MEMS shutter display element, an optical-interference-typeMEMS display element, an electrowetting element, a piezoelectric ceramicdisplay, and a display element including a carbon nanotube. Displaymedia whose contrast, luminance, reflectivity, transmittance, or thelike is changed by electrical or magnetic effect may be included.

Note that examples of display devices having EL elements include an ELdisplay. Examples of a display device including an electron emitterinclude a field emission display (FED), an SED-type flat panel display(SED: surface-conduction electron-emitter display), and the like.Examples of display devices including liquid crystal elements include aliquid crystal display (e.g., a transmissive liquid crystal display, atransflective liquid crystal display, a reflective liquid crystaldisplay, a direct-view liquid crystal display, or a projection liquidcrystal display). Examples of a display device including electronic ink,or an electrophoretic element include electronic paper. In the case of atransflective liquid crystal display or a reflective liquid crystaldisplay, some of or all of pixel electrodes function as reflectiveelectrodes. For example, some or all of pixel electrodes are formed tocontain aluminum, silver, or the like. In such a case, a memory circuitsuch as an SRAM can be provided under the reflective electrodes. Thus,the power consumption can be further reduced.

Note that in the case of using an LED, graphene or graphite may beprovided under an electrode or a nitride semiconductor of the LED.Graphene or graphite may be a multilayer film in which a plurality oflayers are stacked. As described above, provision of graphene orgraphite enables easy formation of a nitride semiconductor thereover,such as an n-type GaN semiconductor including crystals. Furthermore, ap-type GaN semiconductor including crystals or the like can be providedthereover, and thus the LED can be formed. Note that an MN layer may beprovided between the n-type GaN semiconductor including crystals andgraphene or graphite. The GaN semiconductors included in the LED may beformed by MOCVD. Note that when the graphene is provided, the GaNsemiconductors included in the LED can also be formed by a sputteringmethod.

The structures described in this embodiment can be used in appropriatecombination with any of the structures described in the otherembodiments.

Embodiment 16

In this embodiment, electronic devices each including the transistor orthe like of one embodiment of the present invention will be described.

<Electronic Device>

The semiconductor device of one embodiment of the present invention canbe used for display devices, personal computers, or image reproducingdevices provided with recording media (typically, devices whichreproduce the content of recording media such as digital versatile discs(DVDs) and have displays for displaying the reproduced images). Otherexamples of electronic devices that can be equipped with thesemiconductor device of one embodiment of the present invention aremobile phones, game machines including portable game consoles, portabledata terminals, e-book readers, cameras such as video cameras anddigital still cameras, goggle-type displays (head mounted displays),navigation systems, audio reproducing devices (e.g., car audio systemsand digital audio players), copiers, facsimiles, printers, multifunctionprinters, automated teller machines (ATM), and vending machines. FIGS.53A to 53F illustrate specific examples of these electronic devices.

FIG. 53A illustrates a portable game console including a housing 901, ahousing 902, a display portion 903, a display portion 904, a microphone905, a speaker 906, an operation key 907, a stylus 908, and the like.Although the portable game console in FIG. 53A has the two displayportions 903 and 904, the number of display portions included in aportable game console is not limited to this.

FIG. 53B illustrates a portable data terminal including a first housing911, a second housing 912, a first display portion 913, a second displayportion 914, a joint 915, an operation key 916, and the like. The firstdisplay portion 913 is provided in the first housing 911, and the seconddisplay portion 914 is provided in the second housing 912. The firsthousing 911 and the second housing 912 are connected to each other withthe joint 915, and the angle between the first housing 911 and thesecond housing 912 can be changed with the joint 915. An image on thefirst display portion 913 may be switched in accordance with the angleat the joint 915 between the first housing 911 and the second housing912. A display device with a position input function may be used as atleast one of the first display portion 913 and the second displayportion 914. Note that the position input function can be added byproviding a touch panel in a display device. Alternatively, the positioninput function can be added by providing a photoelectric conversionelement called a photosensor in a pixel portion of a display device.

FIG. 53C illustrates a notebook personal computer, which includes ahousing 921, a display portion 922, a keyboard 923, a pointing device924, and the like.

FIG. 53D illustrates an electric refrigerator-freezer, which includes ahousing 931, a door for a refrigerator 932, a door for a freezer 933,and the like.

FIG. 53E illustrates a video camera, which includes a first housing 941,a second housing 942, a display portion 943, operation keys 944, a lens945, a joint 946, and the like. The operation keys 944 and the lens 945are provided for the first housing 941, and the display portion 943 isprovided for the second housing 942. The first housing 941 and thesecond housing 942 are connected to each other with the joint 946, andthe angle between the first housing 941 and the second housing 942 canbe changed with the joint 946. Images displayed on the display portion943 may be switched in accordance with the angle at the joint 946between the first housing 941 and the second housing 942.

FIG. 53F illustrates a car including a car body 951, wheels 952, adashboard 953, lights 954, and the like.

The structures described in this embodiment can be used in appropriatecombination with any of the structures described in the otherembodiments.

Embodiments of the present invention have been described in the aboveembodiments. Note that one embodiment of the present invention is notlimited thereto. That is, various embodiments of the invention aredescribed in this embodiment and the like, and one embodiment of thepresent invention is not limited to a particular embodiment. Forexample, an example in which a channel formation region, source anddrain regions, and the like of a transistor include an oxidesemiconductor is described as one embodiment of the present invention;however, one embodiment of the present invention is not limited to thisexample. Alternatively, depending on circumstances or conditions,various semiconductors may be included in various transistors, a channelformation region of a transistor, a source region or a drain region of atransistor, or the like of one embodiment of the present invention.Depending on circumstances or conditions, at least one of silicon,germanium, silicon germanium, silicon carbide, gallium arsenide,aluminum gallium arsenide, indium phosphide, gallium nitride, an organicsemiconductor, and the like may be included in various transistors, achannel formation region of a transistor, a source region or a drainregion of a transistor, or the like of one embodiment of the presentinvention. Alternatively, depending on circumstances or conditions, anoxide semiconductor is not necessarily included in various transistors,a channel formation region of a transistor, a source region or a drainregion of a transistor, or the like of one embodiment of the presentinvention, for example.

Example 1

In Example 1, the planarity of a sample 1A in the case of forming thesample 1A over an oxide was evaluated.

First, a method for forming an example sample 1A and a comparativesample 1B will be described.

First, a thermal oxide was formed over the silicon wafer as a siliconoxide film. The thermal oxide was formed to a thickness of 100 nm at950° C. in an oxygen atmosphere containing HCl at 3 vol %.

Next, an oxide was formed over the thermal oxide as the sample 1A withuse of the sputtering apparatus including the collimator illustrated inFIG. 21. The oxide was formed using the target of In:Ga:Zn=1:1:1 [atomicratio] in a mixed atmosphere of argon and oxygen (argon at 30 sccm andoxygen at 15 sccm) under the conditions where the pressure was 0.7 Pa, apower supply (DC) of 0.5 kW was applied, the distance between the targetand the substrate was 160 mm, and the substrate temperature was 300° C.Note that a collimator with a thickness of 16 mm was provided so thatthe distance between the target and the collimator was 52 mm and thedistance between the collimator and the substrate was 92 mm, whereby thedistance between the target and the substrate became 160 mm.

Furthermore, an oxide was formed over the thermal oxide as thecomparative sample 1B with use of a sputtering apparatus not including acollimator. The oxide was formed using the target of In:Ga:Zn=1:1:1[atomic ratio] in a mixed atmosphere of argon and oxygen (argon at 30sccm and oxygen at 15 sccm) under the conditions where the pressure was0.7 Pa, a power supply (DC) of 0.5 kW was applied, the distance betweenthe target and the substrate became 160 mm, and the substratetemperature was 300° C.

Through the above steps, the sample 1A and the comparative sample 1Bwere formed.

The planarities of the fabricated sample 1A and the comparative sample1B were evaluated with a scanning probe microscope SPA-500 manufacturedby SII Nano Technology Inc. Conditions of the measurement with thescanning probe microscope were as follows: the scan rate was 1.0 Hz, themeasurement area was 1 μm×1 μm, and the number of data was X=512 andY=512. The number of measurement points was 2. Here, the measurement wasconducted by a method for measuring the surface shape of a sample in astate where a cantilever is resonated while the distance between a probeand the sample is controlled so that the vibration amplitude of thecantilever is maintained constant.

The planarities of the sample 1A and comparative sample 1B wereevaluated using the average plane roughness (Ra), the maximumpeak-to-valley height (P-V), and a root-mean-square roughness (RMS).Here, the average surface roughness (R_(a)) is obtained bythree-dimension expansion of arithmetic means surface roughness R_(a)which is defined by JIS B 0601:2001 (ISO 4287:1997) so that R_(a) can beapplied to a curved surface, and is an average value of the absolutevalues of deviations from a reference surface to a specific surface. Themaximum peak-to-valley height (P-V) is a difference between the heightof the highest peak and the height of the lowest valley in the specificsurface. The peak and the valley refer to a peak and a valley obtainedby three-dimensional expansion of the “peak” and the “valley” defined byJISB0601:2001 (ISO4287:1997). The peak refers to the highest point ofthe peaks in the specific surface. The valley refers to the lowest pointof the valleys in the specific surface.

Results of planarity evaluation of the reprocessed semiconductorsubstrates with the scanning probe microscope are shown in Table 1.

TABLE 1 Collimator Ra[nm] P-V[nm] RMS[nm] Sample 1A used 0.2658 3.7740.3358 Comparative Sample 1B not used 0.6456 8.007 0.8648

FIG. 54A shows an image of a surface shape of the sample 1A. FIG. 54Bshows an image of a surface shape of the comparative sample 1B.

The results show that the sample 1A can be formed with higher planaritythan the comparative sample 1B. Accordingly, the use of the sputteringapparatus is found to be effective in manufacturing a transistor. Notethat the structure shown in this example can be combined as appropriatewith any of the structures shown in the other embodiments and the otherexamples.

Example 2

In this example, the shape of a peripheral region of a channel formationregion was evaluated on the assumption of the transistor structure 1described in Embodiment 1.

First, a method for fabricating example samples 2A to 2D is described.

First, a 100-nm-thick first silicon oxynitride film was formed by aplasma CVD method. The first silicon oxynitride film was formed usingsilane at a flow rate of 5 sccm and dinitrogen monoxide at a flow rateof 1000 sccm as deposition gases under the conditions where the pressurein a reaction chamber was 133.30 Pa, the substrate temperature was 325□C, and a high frequency (RF) power of 13.56 W was applied.

Then, a 20-nm-thick first oxide and a 15-nm-thick second oxide werestacked over the first silicon oxynitride film by a sputtering method.The first oxide was formed using a target containing In, Ga, and Zn atan atomic ratio of 1:3:4 in a mixed atmosphere of argon and oxygen(argon at 40 sccm and oxygen at 5 sccm) under the conditions where thepressure was 0.7 Pa, a power supply (DC) of 0.5 kW was applied, thedistance between the target and the substrate was 60 mm, and thesubstrate temperature was 200° C. The second oxide was formed using atarget containing In, Ga, and Zn at an atomic ratio of 4:2:4.1 in amixed atmosphere of argon and oxygen (argon at 30 sccm and oxygen at 15sccm) under the conditions where the pressure was 0.7 Pa, a power supply(DC) of 0.5 kW was applied, the distance between the target and thesubstrate was 60 mm, and the substrate temperature was 300° C.

Next, a 20-nm-thick first tungsten film was formed over the second oxideby a sputtering method using a tungsten target in an atmosphere of argon(Ar) at a flow rate of 80 sccm as a deposition gas under the conditionswhere the pressure was 0.8 Pa, the substrate temperature was 130° C.,the distance between the target and the substrate was 60 mm, and a powersupply (DC) of 1.0 kW was applied.

Next, a resist mask was formed over the first tungsten film, and thefirst tungsten film was processed by ICP etching to be divided into asecond tungsten film and a third tungsten film. The etching wasperformed in a mixed atmosphere of carbon tetrafluoride (CF₄) at a flowrate of 40 sccm and a chlorine (Cl₂) at a flow rate of 60 sccm under theconditions where the power supply was 2000 W, the bias power was 50 W,the pressure was 0.67 Pa, and the substrate temperature was −10° C.

Then, with the use of the second tungsten film and the third tungstenfilm as masks, the first oxide and the second oxide were processed intoisland shapes by ICP etching performed three times. The first etchingwas performed in a mixed atmosphere of carbon tetrafluoride (CF₄) at aflow rate of 16 sccm and argon (Ar) at a flow rate of 32 sccm under theconditions where the power supply was 600 W, the bias power was 50 W,the pressure was 3.0 Pa and the substrate temperature was 40 □C. Thesecond etching was performed in a mixed atmosphere of carbontetrafluoride (CF₄) at a flow rate of 16 sccm and argon (Ar) at a flowrate of 32 sccm under the conditions where the power supply was 600 W,the bias power was 50 W, the pressure was 1.0 Pa, and the substratetemperature was 40° C. The third etching was performed in an atmosphereof oxygen (O₂) at a flow rate of 200 sccm under the conditions where thepower supply was 2000 W, the bias power was 50 W, the pressure was 0.67Pa, and the substrate temperature was 40° C.

Next, a 320-nm-thick second silicon oxynitride film was formed by aplasma CVD method. The second silicon oxynitride film was formed usingsilane at a flow rate of 5 sccm and dinitrogen monoxide at a flow rateof 1000 sccm as source gases under the conditions where the pressure ina reaction chamber was 133.30 Pa, the substrate temperature was 325 □C,and a high frequency (RF) power of 13.56 W was applied.

Then, planarization treatment was performed on a top surface of thesecond silicon oxynitride film by a CMP method. The planarizationtreatment was performed so that the thickness of the second siliconoxynitride film was reduced by 220 nm, whereby the thickness of thesecond silicon oxynitride film becomes 100 nm.

The polishing conditions in the CMP method were as follows. As apolishing cloth, IC1000/SUBA (registered trademark) using polyurethanefoam, which was produced by Nitta Haas Incorporated, was used. Asslurry, Semi-Sperse (registered trademark) 25 using fumed silica, whichwas produced by Cabot Microelectronics, was used. The flow rate of theslurry was 150 mL/min and the polishing pressure was 3.6 psi. Thenumbers of rotations of a polishing head and a table were 93 rpm and 90rpm, respectively. The polishing treatment was performed while theprocessed object was attached to the polishing head and the polishingcloth was attached to the table. After the polishing, megasonic cleaningwas performed.

Next, a 30-nm-thick fourth tungsten film was formed over the secondsilicon oxynitride film by a sputtering method using a tungsten targetin an atmosphere of argon (Ar) at a flow rate of 80 sccm as a depositiongas under the conditions where the pressure was 0.8 Pa, the substratetemperature was 130° C., the distance between the target and thesubstrate was 60 mm, and a power supply (DC) of 1.0 kW was applied.

Next, a 50-nm-thick third silicon oxynitride film was formed by a plasmaCVD method. The third silicon oxynitride film was formed using silane ata flow rate of 5 sccm and dinitrogen monoxide at a flow rate of 1000sccm as deposition gases under the conditions where the pressure in areaction chamber was 133.30 Pa, the substrate temperature was 325 □C,and a high frequency (RF) power of 13.56 W was applied.

Next, a resist mask was formed over the third silicon oxynitride filmand the fourth tungsten film, and the third silicon oxynitride film andthe fourth tungsten film were processed by ICP etching performed fourtimes. The first etching was performed in an atmosphere of carbontetrafluoride (CF₄) at a flow rate of 80 sccm under the conditions wherethe power supply was 500 W, the bias power was 100 W, the pressure was3.0 Pa, and the substrate temperature was 40° C. The second etching wasperformed in a mixed atmosphere of carbon tetrafluoride (CF₄) at a flowrate of 67 sccm and oxygen (O₂) at a flow rate of 13 sccm under theconditions where the power supply was 550 W, the bias power was 350 W,the pressure was 5.3 Pa, and the substrate temperature was 40° C. Thethird etching was performed in a mixed atmosphere of carbontetrafluoride (CF₄) at a flow rate of 22 sccm and oxygen (O₂) at a flowrate of 22 sccm under the conditions where the power supply was 1000 W,the bias power was 100 W, the pressure was 1.3 Pa, and the substratetemperature was 40° C. The fourth etching was performed in a mixedatmosphere of carbon tetrafluoride (CF₄) at a flow rate of 22 sccm andoxygen (O₂) at a flow rate of 22 sccm under the conditions where thepower supply was 1000 W, the bias power was 100 W, the pressure was 1.3Pa, and the substrate temperature was 40° C. A hard mask was formedusing the fourth tungsten film by the etching process.

Next, with the use of the hard mask, an opening was formed in the secondsilicon oxynitride film by ICP etching. The etching was performed in amixed atmosphere of argon (Ar) at a flow rate of 800 sccm, oxygen (O₂)at a flow rate of 30 sccm, and carbon tetrafluoride (CF₄) at a flow rateof 22 sccm under the conditions where the power supply was 5000 W, thebias power was 1150 W, the pressure was 3.37 Pa, and the substratetemperature was 40° C.

Here, an opening A was formed in an example sample 2A. An opening B wasformed in an example sample 2B. An opening C was formed in an examplesample 2C. An opening D was formed in an example sample 2D. The sizes ofthe openings A to D are different from each other.

Next, a hard mask was removed by ICP etching performed three times. Thefirst etching was performed in a mixed atmosphere of carbontetrafluoride (CF₄) at a flow rate of 22 sccm, oxygen (O₂) at a flowrate of 22 sccm, and chlorine (Cl₂) at a flow rate of 11 sccm under theconditions where the power supply was 1000 W, the bias power was 50 W,the pressure was 1.3 Pa, and the substrate temperature was 40° C. Thesecond etching was performed in a mixed atmosphere of carbontetrafluoride (CF₄) at a flow rate of 22 sccm, oxygen (O₂) at a flowrate of 22 sccm, and chlorine (Cl₂) at a flow rate of 11 sccm under theconditions where the power supply was 1000 W, the bias power was 50 W,the pressure was 1.3 Pa, and the substrate temperature was 40° C. Thethird etching was performed in an atmosphere of oxygen (O₂) at a flowrate of 100 sccm under the conditions where the power supply was 500 W,the bias power was 100 W, the pressure was 1.3 Pa, and the substratetemperature was 40° C.

Next, a 10-nm-thick third oxide was formed on each of the second siliconoxynitride film having openings A to D with the use of the sputteringapparatus including the collimator illustrated in FIG. 21. The thirdoxide was formed using the target of In:Ga:Zn=1:3:2 [atomic ratio] in amixed atmosphere of argon and oxygen (argon at 30 sccm and oxygen at 15sccm) under the conditions where the pressure was 0.7 Pa, a power supply(DC) of 0.5 kW was applied, the distance between the target and thesubstrate was 160 mm, and the substrate temperature was 200° C. Notethat a collimator with a thickness of 16 mm was provided so that thedistance between a target and the collimator was 52 mm and the distancebetween the collimator and the substrate was 92 mm, whereby the distancebetween the target and the substrate was 160 mm.

Through the above steps, the example samples 2A to 2D were formed.

Next, cross sections of the example samples 2A to 2D were observed.FIGS. 55A to 55D are bright-filed images of the example samples 2A to2D, which were obtained with a scanning transmission electron microscope(STEM). The example samples 2A to 2C are each a cross-sectional view ofan island-shaped oxide in the longitudinal direction, and the examplesample 2D is a cross-sectional view of an island-shaped oxide in thelateral direction.

In the opening A in the example sample 2A, the distance between thesecond tungsten film and the third tungsten film is 32.1 nm, and thethird oxide is formed on a side surface of the second silicon oxynitridefilm and the second oxide.

In the opening B in the example sample 2B, the distance between thesecond tungsten film and the third tungsten film is 56.7 nm, and thethird oxide is formed on a side surface of the second silicon oxynitridefilm and the second oxide.

In the opening C in the example sample 2C, the distance between thesecond tungsten film and the third tungsten film is 88.1 nm, and thethird oxide is formed on a side surface of the second silicon oxynitridefilm and the second oxide.

In the opening D in the example sample 2D, the third oxide is formed ona side surface of the second silicon oxynitride film, the second oxide,and the first silicon oxynitride film.

The results of the STEM images in FIGS. 55A to 55D show that the examplesamples 2A to 2D fabricated in this example each have a favorablecross-sectional shape. It is found that a film can be formed even on abottom surface of the minute opening in the example sample 2A. It isalso found that the film is formed thinner on the side surface of theopening than on the bottom surface thereof.

The structure described above in this example can be combined with anyof the structures described in the other embodiments and examples asappropriate.

EXPLANATION OF REFERENCE

100: target, 101: sputtering apparatus, 110: backing plate, 120: targetholder, 130: magnet unit, 130N: magnet, 130S: magnet, 132: magnetholder, 150: collimator, 151: movable portion, 152: movable portion,160: substrate, 170: substrate stage, 180 a: magnetic force line, 180 b:magnetic force line, 190: member, 200: imaging device, 201: switch, 202:switch, 203: switch, 210: pixel portion, 211: pixel, 212: subpixel,212B: subpixel, 212G: subpixel, 212R: subpixel, 220: photoelectricconversion element, 230: pixel circuit, 231: wiring, 247: wiring, 248:wiring, 249: wiring, 250: wiring, 253: wiring, 254: filter, 254B:filter, 254G: filter, 254R: filter, 255: lens, 256: light, 257: wiring,260: peripheral circuit, 270: peripheral circuit, 280: peripheralcircuit, 290: peripheral circuit, 291: light source, 300: siliconsubstrate, 310: layer, 320: layer, 330: layer, 340: layer, 351:transistor, 352: transistor, 353: transistor, 360: photodiode, 361:anode, 363: low-resistance region, 370: plug, 371: wiring, 372: wiring,373: wiring, 380: insulator, 400: substrate, 401: insulator, 402:insulator, 404: conductor, 404 a: conductor, 404 b: conductor, 406 a:insulator, 406 b: semiconductor, 406 c: insulator, 406 d: insulator,408: insulator, 410: insulator, 412: insulator, 413: conductor, 414:mixed region, 416: conductor, 416 a: conductor, 416 b: conductor, 420:conductor, 430: resist mask, 431: resist mask, 450: semiconductorsubstrate, 452: insulator, 454: conductor, 456: region, 460: region,462: insulator, 464: insulator, 466: insulator, 468: insulator, 472 a:region, 472 b: region, 474 a: conductor, 474 b: conductor, 474 c:conductor, 476 a: conductor, 476 b: conductor, 478 a: conductor, 478 b:conductor, 478 c: conductor, 480 a: conductor, 480 b: conductor, 480 c:conductor, 489: insulator, 490: insulator, 492: insulator, 493:insulator, 494: insulator, 495: insulator, 496 a: conductor, 496 b:conductor, 496 c: conductor, 496 d: conductor, 496 e: conductor, 496 f:conductor, 498 a: conductor, 498 b: conductor, 498 c: conductor, 504:conductor, 507 a: conductor, 507 b: conductor, 511: insulator, 514:conductor, 515: conductor, 516: conductor, 521: routing switch element,522: logic element, 523: configuration memory, 524: lookup table, 525:register, 526: selector, 527: configuration memory, 700: substrate, 701:insulator, 702 a: conductor, 702 b: conductor, 703: insulator, 704:insulator, 705: semiconductor, 705 a: region, 706: insulator, 707:insulator, 707 a: conductor, 707 b: conductor, 708: conductor, 709:conductor, 716: insulator, 719: light-emitting element, 720: insulator,721: insulator, 731: terminal, 732: FPC, 733 a: wiring, 734: sealant,735: driver circuit, 736: driver circuit, 737: pixel, 741: transistor,742: capacitor, 743: switching element, 744: signal line, 750:substrate, 751: transistor, 752: capacitor, 753: liquid crystal element,754: scan line, 755: signal line, 781: conductor, 782: light-emittinglayer, 783: conductor, 784: partition wall, 791: conductor, 792:insulator, 793: liquid crystal layer, 794: insulator, 795: spacer, 796:conductor, 797: substrate, 901: housing, 902: housing, 903: displayportion, 904: display portion, 905: microphone, 906: speaker, 907:operation key, 908: stylus, 911: housing, 912: housing, 913: displayportion, 914: display portion, 915: joint, 916: operation key, 921:housing, 922: display portion, 923: keyboard, 924: pointing device, 931:housing, 932: door for a refrigerator, 933: door for a freezer, 941:housing, 942: housing, 943: display portion, 944: operation keys, 945:lens, 946: joint, 951: car body, 952: wheels, 953: dashboard, 954:lights, 1000: IC, 1189: ROM interface, 1190: substrate, 1191: ALU, 1192:ALU controller, 1193: instruction decoder, 1194: interrupt controller,1195: timing controller, 1196: register, 1197: register controller,1198: bus interface, 1199: ROM, 1200: memory element, 1201: circuit,1202: circuit, 1203: switch, 1204: switch, 1206: logic element, 1207:capacitor, 1208: capacitor, 1209: transistor, 1210: transistor, 1213:transistor, 1214: transistor, 1220: circuit, 1700: deposition apparatus,1701: atmosphere-side substrate supply chamber, 1702: atmosphere-sidesubstrate transfer chamber, 1703 a: load lock chamber, 1703 b: unloadlock chamber, 1704: transfer chamber, 1705: substrate-heating chamber,1706 a: deposition chamber, 1706 b: deposition chamber, 1706 c:deposition chamber, 1751: cryotrap, 1752: substrate delivery stage,1761: cassette port, 1762: alignment port, 1763 a: transfer robot, 1763b: transfer robot, 1764: gate valve, 1765: heating stage, 1770: vacuumpump, 1771: cryopump, 1772: turbo molecular pump, 1780: mass flowcontroller, 1781: refiner, 1782: gas heating system, 2100: transistor,2200: transistor, 2700: manufacturing apparatus, 2701: atmosphere-sidesubstrate supply chamber, 2702: atmosphere-side substrate transferchamber, 2703 a: load lock chamber, 2703 b: unload lock chamber, 2704:transfer chamber, 2706 a: chamber, 2706 b: chamber, 2706 c: chamber,2706 d: chamber, 2761: cassette port, 2762: alignment port, 2763 a:transfer robot, 2763 b: transfer robot, 2801: gas supply source, 2802:valve, 2803: high-frequency generator, 2804: waveguide, 2805: modeconverter, 2806: gas pipe, 2807: waveguide, 2808: slot antenna plate,2809: dielectric plate, 2810: high-density plasma, 2811: substrate,2812: substrate stage, 2813: heating mechanism, 2815: matching box,2816: high-frequency power source, 2817: vacuum pump, 2818: valve, 2819:exhaust port, 2820: lamp, 2821: gas supply source, 2822: valve, 2823:gas inlet, 2824: substrate, 2825: substrate stage, 2826: heatingmechanism, 2828: vacuum pump, 2829: valve, 2830: exhaust port, 3001:wiring, 3002: wiring, 3003: wiring, 3004: wiring, 3005: wiring, 3200:transistor, 3300: transistor, 3400: capacitor, 4001: wiring, 4003:wiring, 4005: wiring, 4006: wiring, 4007: wiring, 4008: wiring, 4009:wiring, 4021: layer, 4022: layer, 4023: layer, 4100: transistor, 4200:transistor, 4300: transistor, 4400: transistor, 4500: capacitor, 4600:capacitor, 5100: pellet, 5120: substrate, 5161: region

This application is based on Japanese Patent Application serial no.2015-081993 filed with Japan Patent Office on Apr. 13, 2015, andJapanese Patent Application serial no. 2015-082008 filed with JapanPatent Office on Apr. 13, 2015, the entire contents of which are herebyincorporated by reference.

1. A semiconductor device, comprising: a semiconductor over a substrate;a first conductor and a second conductor over the semiconductor; a firstinsulator over the first conductor and the second conductor; a secondinsulator over the semiconductor; a third insulator over the secondinsulating; a third conductor over the third insulating; and a fourthconductor over the third conductor, wherein the third insulator has aregion in contact with a side surface of the first insulator, whereinthe third conductor and the fourth conductor have a function as a gateelectrode, wherein the semiconductor has a first region overlapping abottom surface of the first conductor, a second region overlapping abottom surface of the second conductor, and a third region overlapping abottom surface of the third conductor, and wherein a length between atop surface of the semiconductor and the bottom surface of the thirdconductor is greater than the length between the first region and thethird region.
 2. A semiconductor device, comprising: a semiconductorover a substrate; a first conductor and a second conductor over thesemiconductor; a first insulator over the first conductor and the secondconductor; a second insulator over the semiconductor; a third insulatorover the second insulating; a third conductor over the third insulating;a fourth conductor over the third conductor; and a fifth conductorbetween the substrate and the semiconductor, wherein the third insulatorhas a region in contact with a side surface of the first insulator,wherein the third conductor and the fourth conductor have a function asa gate electrode, wherein the fifth conductor has a region overlappingwith the third conductor and the fourth conductor, wherein thesemiconductor has a first region overlapping a bottom surface of thefirst conductor, a second region overlapping a bottom surface of thesecond conductor, and a third region overlapping a bottom surface of thethird conductor, and wherein a length between a top surface of thesemiconductor and the bottom surface of the third conductor is greaterthan the length between the first region and the third region.
 3. Asemiconductor device, comprising: a semiconductor over a substrate; afirst conductor and a second conductor over the semiconductor; a firstinsulator over the first conductor and the second conductor; a secondinsulator over the semiconductor; a third insulator over the secondinsulating; a third conductor over the third insulating; and a fourthconductor over the third conductor, wherein the third insulator has aregion in contact with a side surface of the first insulator, whereinthe semiconductor has a first region overlapping a bottom surface of thefirst conductor, a second region overlapping a bottom surface of thesecond conductor, and a third region overlapping a bottom surface of thethird conductor, and wherein a length between a top surface of thesemiconductor and the bottom surface of the third conductor is greaterthan the length between the first region and the third region.
 4. Thesemiconductor device according to claim 1, wherein the semiconductor isan oxide semiconductor.
 5. The semiconductor device according to claim2, wherein the semiconductor is an oxide semiconductor.
 6. Thesemiconductor device according to claim 3, wherein the semiconductor isan oxide semiconductor.
 7. The semiconductor device according to claim4, wherein the oxide semiconductor comprises indium, gallium, and zinc.8. The semiconductor device according to claim 5, wherein the oxidesemiconductor comprises indium, gallium, and zinc.
 9. The semiconductordevice according to claim 6, wherein the oxide semiconductor comprisesindium, gallium, and zinc.
 10. The semiconductor device according toclaim 7, wherein the oxide semiconductor is polycrystalline, a CAAC-OS,a nc-OS, or an a-like OS.
 11. The semiconductor device according toclaim 8, wherein the oxide semiconductor is polycrystalline, a CAAC-OS,a nc-OS, or an a-like OS.
 12. The semiconductor device according toclaim 9, wherein the oxide semiconductor is polycrystalline, a CAAC-OS,a nc-OS, or an a-like OS.